W Etch - 40nm BSI CMOS Image Sensor 40nm

Strict control of the W etch profile is required because aspect ratio dependent etching (ARDE) or RIE-lag can lead to incomplete metal clearance in dense arrays .

The W Etch step in the MET0 module of a 40nm BSI CMOS Image Sensor directly follows lithographic patterning and is responsible for def

ining the first level of local interconnects . Tungsten is widely used in integrated circuits as metal interconnects and diffusion barriers due to its excellent step coverage and electromigration resistance . In this specific process flow, a blanket CVD W layer has been deposited over the wafer, and the Metal 0 photoresist mask defines the desired circuit layout . The primary objective of the W Etch step is to selectively remove the exposed tungsten while preserving the patterned lines, thereby isolating adjacent metal tracks and preparing the structure for subsequent ashing, cleaning, and PMD 4 dielectric deposition . The etching of tungsten is fundamentally driven by reactive ion etching (RIE), which relies on the synergistic action of chemical surface reactions and physical ion bombardment . High-density plasma generates neutral reactive radicals that dominate the chemical reaction, forming volatile byproducts with the metal, while charged ions accelerated by the electric field provide directional kinetic energy . This directional ion bombardment enhances surface reactions at the trench bottom and suppresses lateral etching, enabling the formation of highly vertical sidewall profiles critical for dense nanoscale features . Balancing the chemical etching by reactive gas species with the physical sputtering caused by ion bombardment ultimately determines both the overall etch rate and the degree of pattern anisotropy . Fluorine-based chemistries (such as SF6) are typically selected for W etching because they provide high chemical reactivity, though they can suffer from isotropic behavior if the neutral radicals dominate the reaction . To counteract mask undercut and profile bowing, passivation gases are optimized to protect the sidewalls during the main etch process, functioning similarly to the cyclic protection mechanisms seen in advanced atomic layer etching schemes . The bias voltage applied to the wafer controls the incident ion energy, directly influencing both the W etch rate and the selectivity to the underlying adhesion layer, typically TiN . If the ion energy is driven too high to accelerate the process, the excessive physical sputtering can degrade the W:TiN selectivity and induce severe plasma-induced surface damage to the underlying layers . At the 40nm node, the resistance-capacitance (RC) delay and interconnect reliability are tightly coupled to the dimensional fidelity of the MET0 lines, as device speed and power consumption are highly sensitive to parasitic elements . Strict control of the W etch profile is required because aspect ratio dependent etching (ARDE) or RIE-lag can lead to incomplete metal clearance in dense arrays . Furthermore, minimizing plasma-induced damage during the etch is essential to preserve the structural integrity of the underlying barrier metal, which directly affects the crystalline structure and reliability of the overall interconnect stack .

[High] Mask Undercut and CD Loss: Isotropic etching driven by non-directional neutral species (such as fluorine radicals) can attack the tungsten sidewalls underneath the photoresist mask . If the passivation mechanism is insufficient to protect the newly exposed sidewalls, lateral chemical etching outpaces directional ion etching, resulting in narrowed MET0 lines and increased interconnect resistance .
[High] Poor Selectivity to Underlying Barrier (TiN): Excessive wafer bias increases the kinetic energy of bombarding ions, which exacerbates the physical sputtering component of the plasma . This can result in punching through the underlying TiN adhesion/barrier layer, which subsequently degrades interconnect reliability and compromises the interface for subsequent processing .
[Medium] RIE-Lag and Incomplete Etch in Dense Arrays: In structures with varying aspect ratios, the transport of neutral radicals and the extraction of volatile byproducts are hindered in narrow spaces, a mass-transport phenomenon known as the RIE-lag effect . This causes the etch rate in dense MET0 trenches to be significantly slower than in isolated areas, potentially leaving unetched tungsten residue that causes electrical short circuits .
[Low] Plasma-Induced Surface Damage: High-energy ions from the plasma discharge strike the wafer surface and transfer kinetic energy directly into the crystal lattice . This energetic bombardment can create physical defects, dislocations, or dangling bonds in the exposed underlying dielectric or barrier materials, leading to degraded device electrical properties and increased leakage paths .

Strict control of the W etch profile is required because aspect ratio dependent etching (ARDE) or RIE-lag can lead to incomplete metal clearance in dense arrays .

The W Etch step in the MET0 module of a 40nm BSI CMOS Image Sensor directly follows lithographic patterning and is responsible for def

[High] Mask Undercut and CD Loss: Isotropic etching driven by non-directional neutral species (such as fluorine radicals) can attack the tungsten sidewalls underneath the photoresist mask . If the passivation mechanism is insufficient to protect the newly exposed sidewalls, lateral chemical etching outpaces directional ion etching, resulting in narrowed MET0 lines and increased interconnect resistance .
[High] Poor Selectivity to Underlying Barrier (TiN): Excessive wafer bias increases the kinetic energy of bombarding ions, which exacerbates the physical sputtering component of the plasma . This can result in punching through the underlying TiN adhesion/barrier layer, which subsequently degrades interconnect reliability and compromises the interface for subsequent processing .
[Medium] RIE-Lag and Incomplete Etch in Dense Arrays: In structures with varying aspect ratios, the transport of neutral radicals and the extraction of volatile byproducts are hindered in narrow spaces, a mass-transport phenomenon known as the RIE-lag effect . This causes the etch rate in dense MET0 trenches to be significantly slower than in isolated areas, potentially leaving unetched tungsten residue that causes electrical short circuits .
[Low] Plasma-Induced Surface Damage: High-energy ions from the plasma discharge strike the wafer surface and transfer kinetic energy directly into the crystal lattice . This energetic bombardment can create physical defects, dislocations, or dangling bonds in the exposed underlying dielectric or barrier materials, leading to degraded device electrical properties and increased leakage paths .

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges

40nm BSI CMOS Image SensorPreview

Process Cross-Section

Step highlight

In depth

Risks & Challenges