The high-density plasma generates an ion flux that provides the directionality needed for anisotropic etching by breaking chemical bonds on the exposed oxide surface .
In depth
The Upper OCL Coating Etch step serves to create a precise physical opening in the uppermost protective oxide layer to expose the
underlying structures for subsequent packaging or bonding connections . This step immediately follows the first photoresist patterning phase, which defines the geometric coverage of the pad opening (Engineering Practice). Positioned prior to the Ashing and second Bond Pad Opening steps, this process specifically targets the thick upper protective oxide while preserving the underlying grid seal layer . This carefully staged approach distinguishes the Upper OCL Coating Etch from the subsequent Upper Grid Seal Layer Etch, as the latter removes the final hermetic barrier, whereas this current step handles the bulk removal of the outer optical or planarization dielectric . Furthermore, it differs from the Lower OCL Coating Etch by operating at the highest topological level of the wafer, interacting directly with package-level stress dynamics . The removal of this protective dielectric is driven by a synergistic combination of physical ion bombardment and chemical radical reactions . The high-density plasma generates an ion flux that provides the directionality needed for anisotropic etching by breaking chemical bonds on the exposed oxide surface . Concurrently, oxygen- and fluorine-containing neutral radicals react with the activated surface to form volatile byproducts, dictating the fundamental etch rate . As the etch progresses downward, geometric shadowing can limit the transport of neutral reactants into the opening, a phenomenon known as aspect-ratio-dependent etching (ARDE) . Furthermore, creating the opening introduces geometric discontinuities between the protective dielectric and the underlying layers, which can generate localized stress singularity fields . To independently control these physical and chemical mechanisms, this process typically employs a dual-frequency confined plasma etcher . The higher frequency RF power primarily governs the electron energy distribution and plasma density, thereby modulating the physical ion flux without excessively altering ion energy . Meanwhile, adjustments to the oxygen and fluorocarbon gas flows directly change the density of chemical radicals, managing the critical balance between etching and protective polymer deposition . Controlling this balance is essential, because excessive polymer buildup can lead to an etch stop, whereas insufficient polymer allows isotropic lateral etching that degrades critical dimensions . The process parameters are also tuned to yield a trapezoidal sidewall profile rather than a strictly vertical one, effectively lowering local stress concentration factors and suppressing crack initiation in the brittle protective layer . In nanoscale Backside Illuminated (BSI) CMOS Image Sensor architectures, packaging constraints often demand highly efficient die area utilization, frequently employing Bond Over Active (BOA) layouts where pads are situated directly above active devices . During subsequent wire bonding or packaging, mechanical loads exert transient high stresses on the top interconnects and underlying low-k dielectrics . Because modern multi-layer metal and dielectric stacks must disperse these loads to protect the fragile silicon active area, the Upper OCL etch profile must prevent the creation of sharp corners that would otherwise amplify stress transfer . By carefully defining the overlap width and sidewall slope of the protective dielectric, the maximum tensile stress is shifted away from sensitive step edges, ensuring robust electro-mechanical reliability during final packaging .
Risks & Challenges
[High] Etch Stop or Blow-out: Drifts in chamber conditions or oxygen radical density alter the delicate balance between fluorocarbon polymer deposition and chemical etching . If polymer deposition outpaces the etch rate, the process prematurely stops; conversely, insufficient polymer protection causes lateral blow-out and loss of critical dimensions .
[Medium] Protective Dielectric Cracking: A highly vertical etch profile creates sharp geometric discontinuities at the pad step, inducing stress singularities and high tensile stress . Under subsequent mechanical or thermal loading, these concentrated stresses can nucleate cracks in the brittle protective dielectric, compromising the hermetic seal .
[Medium] Aspect-Ratio Dependent Etching (ARDE) Lag: As the opening deepens, geometric shadowing restricts the transport-limited delivery of neutral reactants to the etch front . This localized depletion causes smaller or deeper features to etch more slowly than larger ones, potentially leaving residual dielectric on the contacts .
[Low] Plasma-Induced Substrate Damage: Excessive ion bombardment energy, resulting from improper RF bias control, can cause intense physical sputtering at the etch front . This sputtering can severely roughen and damage the underlying stopping layer, negatively impacting subsequent interfacial adhesion or electrical contact .