40nm BSI CMOS Image SensorPreview

ires opening through the backside passivation, optical isolation, and structural dielectric layers to form the bond pad [A2]. The "Optical Pad 1 Etch" is specifically positioned to etch through the upper bulk dielectric or specific hard-mask capping layers before penetrating the underlying structural grids (such as the Oxide Grid Seal Layer) and anti-reflective/passivation stacks (BPMD, HKD/AR2) [A1]. Unlike subsequent Pad 2 and Pad 3 etches which may target different residual materials or utilize modified chemistries to clear specific interface layers, the Pad 1 Etch handles the primary high-rate bulk dielectric removal [P3]. This multi-step, sequenced approach ensures that the pad geometry tapers correctly for subsequent metallization or hybrid bonding integrations, establishing a reliable continuous profile similar to the monolithic pad and TSV structures described in advanced backside connection architectures [A2]. The etching is fundamentally driven by an Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) process, which provides the necessary high-density plasma for efficient removal of oxide-based layers [P1]. The core mechanism relies on the synergy of physical ion bombardment and chemical surface reactions [P3]. High-energy ions, accelerated by an independently controlled substrate bias, bombard the material surface to break silicon-oxygen bonds, while reactive fluorine radicals generated from the fluorocarbon gas phase react with the exposed silicon to form volatile SiFx and COx byproducts [P1]. To maintain a highly anisotropic profile and protect the trench sidewalls from isotropic lateral etching, the fluorocarbon plasma simultaneously deposits a carbon-rich polymer film [P1]. The dynamic competition between the physical sputtering of this passivation layer and the chemical etching of the underlying dielectric dictates the final sidewall verticality and overall etch depth [A1]. Fluorocarbon chemistry is explicitly chosen for this step because it achieves a critical balance between a high oxide etch rate and the necessary etch selectivity against underlying barrier layers [P1]. Adjusting the C/F ratio of the plasma through specific gas mixtures enables robust surface passivation, which significantly reduces the probability of reactive F atoms attacking protected or sensitive surfaces [P1]. In high-density ICP reactors, the over-dissociation of radicals can easily degrade this selectivity; thus, precisely controlling the gas residence time serves as a core parameter to manage the polymerization-to-etching ratio without sacrificing manufacturing throughput [P1]. Furthermore, if an etch-stop layer is utilized within the integrated stack, the chemistry must be carefully tuned so that active radicals rapidly etch the silica while stalling on chemically stable barrier materials, thereby preventing unwanted substrate roughening or device damage [P2]. At the 40nm node, device dimensions necessitate deep and narrow geometries for backside pad connections, intensifying the requirement for precise plasma control [A2]. As device scaling limits the tolerance for subthreshold leakage and electric field concentration [T3], maintaining smooth sidewalls and preventing sharp corners during deep trench or pad formation is paramount to suppress enhanced carrier recombination and dark current degradation in the adjacent pixel arrays [A1]. Therefore, the Pad 1 Etch must carefully decouple plasma generation from ion acceleration to minimize physical damage to the surrounding ultra-thin sensor substrate, ensuring both electrical reliability and optimal optical isolation [P3].