40nm BSI CMOS Image SensorPreview

iode (PPD) [P4]. This implantation utilizes a thick photoresist mask to block energetic ions from the surrounding regions, resulting in heavy ion-bombardment of the resist material [T1]. The current Ashing & Strip/Clean step is essential to completely remove this ion-hardened photoresist prior to the Pixel Array P-Well IIP photolithography sequence (Engineering Practice). Unlike standard post-etch cleans, this specific step must address a resist layer whose structural integrity has been severely altered by high-energy dopant collision cascades [P2]. Complete removal is critical because any residual organics or trapped dopants will degrade the Si-SiO2 interface, which must remain pristine to ensure low average dark current and prevent white spot blemishes in the final image sensor [P3]. The physical removal process relies on a combination of dry plasma ashing and wet chemical cleaning [P2]. During the dry ash phase, oxygen plasma generates highly reactive radicals that oxidize the carbon-based photoresist polymer into volatile byproducts such as CO and CO2 [P2]. Because the high-energy N Photocathode implant depletes hydrogen from the resist surface, a dense, carbon-rich crust forms that resists standard chemical dissolution (Engineering Practice). Therefore, the ashing process must chemically break down and volatilize this specific crust layer [A1]. Following the dry ashing process, a wet strip sequence—typically involving an Ammonia-Hydrogen Peroxide Mixture (APM)—is employed to remove residual inorganic compounds and particles [P2]. The APM solution simultaneously oxidizes trace organics and slightly etches the transient chemical oxide to physically lift off surface particulate contamination (Engineering Practice). The selection of a two-stage dry-wet sequence is dictated by the chemical nature of the post-implant residues [P2]. Standard solvent strips are entirely ineffective against the highly cross-linked, carbonized crust of an ion-implanted resist (Engineering Practice). Furthermore, the dry plasma alone cannot remove inorganic dopant residues or metallic contaminants sputtered onto the wafer during the IIPX process [P2]. The subsequent wet clean must therefore be precisely calibrated to remove these generation-recombination centers without excessively consuming the underlying silicon [P3]. Controlling silicon consumption during this wet clean is vital, analogous to the strict surface controls required in advanced post-etch cleans, to prevent the unintended deepening or shifting of subsequent junction profiles [P2]. In a scaled 40nm BSI CMOS image sensor architecture, the precise control of the photodiode depth and the surface potential pinning layer is exceptionally stringent [P1]. If the ashing and cleaning steps consume too much surface silicon or leave sub-monolayer metallic contaminants, the future high-concentration p+ surface pinning layer will fail to effectively passivate interface states [P1]. This degradation fundamentally compromises the voltage integration capacity of the photodiode and severely diminishes the sensor's robustness to dark current generation [P3].