40nm BSI CMOS Image SensorPreview

nd clean sequence prepares the wafer for the subsequent P+ VSS and Periphery P-Well Contact IIP photolithography step (Engineering Practice). The upstream P-pinning implant is fundamentally responsible for introducing a heavily doped p+ layer at the Si-SiO₂ interface, which starves the interface states of electrons and suppresses dark current [P1]. Any residual organics, polymers, or metallic contaminants left on the surface would not only cause overlay misalignment in the next lithography step but also risk diffusing into the active photodiode during subsequent thermal cycles, thereby severely degrading minority carrier lifetimes [A2]. The physical mechanism of the removal process typically relies on a synergistic combination of dry oxygen-based plasma ashing and a subsequent wet chemical strip [A3]. During the plasma ashing phase, reactive oxygen radicals are generated to continuously oxidize the organic photoresist into volatile compounds, such as CO₂ and H₂O, thereby stripping away the bulk of the masking layer [A1]. However, because the preceding step is a heavily dosed ion implantation, the outermost layer of the photoresist undergoes severe outgassing and cross-linking, transforming into a hardened, carbon-rich crust [A2]. Ashing alone struggles to remove this crust without leaving behind inorganic knock-on residues and hardened polymers [A3]. Therefore, a wet clean, commonly utilizing an SC1 formulation (NH₄OH/H₂O₂/H₂O), is employed to establish an 'oxidation–dissolution' dynamic equilibrium [P2]. In this equilibrium, H₂O₂ continuously oxidizes the underlying substrate to form an ultrathin oxide, while NH₄OH dissolves it at a comparable rate, undercutting and lifting off residual particles [P2]. The selection of cleaning chemistry and process parameters for this step is tightly constrained by the physics of heavily doped semiconductors [T1]. Because the P-pinning implant creates a steep, heavily doped p+ surface profile, the chemical reactivity of the silicon surface is fundamentally altered [P1]. High dopant concentrations increase the local oxidation and dissolution rates in alkaline/oxidizing wet cleans, leading to accelerated volumetric silicon consumption [P2]. If the SC1 temperature, time, or NH₄OH concentration is set too high, the cleaning process will etch away the topmost atomic layers of the critically engineered p+ pinning region [P2]. This unintended etching would directly compromise the steep dopant gradient needed to terminate electric field lines from fixed oxide charges, thereby resurrecting interface-state dark current generation [P1]. Consequently, highly dilute chemistries and strictly bounded process times must be deployed to ensure residue removal without substrate degradation [A3]. What differentiates this specific Ashing & Strip/Clean step from other similar steps in the 40nm flow (such as those following standard well implants) is its direct interaction with the highly sensitive Pinned Photodiode (PPD) and Transfer Gate (TG) regions [A2]. At the 40nm node, the physical boundaries governing charge transfer between the PPD and the Floating Diffusion are engineered at the nanometer scale [T1]. Any surface roughening or non-uniform oxide loss directly over the photodetector alters the surface potential, causing microscopic potential barriers that hinder complete charge transfer and induce image lag [P2]. Thus, this step must execute a perfect chemical balance: maintaining enough oxidative power to eliminate implant-hardened resist while exhibiting near-zero silicon and oxide loss over the image sensor's active core [P2].