40nm BSI CMOS Image SensorPreview

fter PMD 5 Deposition and prior to Metal 1 (M1) Trench photolithography, serves as a critical surface preparation process for the back-end-of-line (BEOL) interconnect integration (Engineering Practice). In advanced nodes, the post-deposition surface profile of dielectrics is highly dependent on underlying pattern geometries, necessitating strict defect control before lithography can proceed [P3]. Unlike pre-epitaxy cleans that focus on removing native oxides to expose a crystalline lattice for epitaxial growth [A3], this specific Pre Litho Cleaning step targets the removal of adventitious particles, organic residues, and airborne molecular contaminants from the newly deposited PMD 5 oxide (Engineering Practice). This ensures a pristine surface for the uniform adhesion of subsequent anti-reflective coating (ARC) and photoresist layers, which is absolutely critical for accurately defining the M1 damascene trench structures [P2]. The cleaning mechanism fundamentally relies on controlled wet-chemical interactions at the dielectric interface [P1]. When processing complex substrates, modern cleaning solutions must carefully balance surface material removal with structural passivation [A1]. For dielectric surfaces, the process typically utilizes dilute wet chemistries to undercut and lift off nanoscale particles through a very slight, self-limiting etching of the topmost oxide layer [P1]. Analogous to the controlled oxidation and dissolution steps utilized in wet atomic layer etching, the etchant concentration must be precisely tuned to avoid excessive surface roughening [P1]. Furthermore, specific buffering agents or typical metal element ions can be introduced into the solvent system to regulate interfacial chemical interactions, preventing aggressive chemical attack on the PMD while effectively stripping adventitious residues [A1]. Concurrently, electrostatic repulsion—governed by modulating the zeta potential between the particles and the substrate via the solution's pH regime—prevents the re-adsorption of suspended particles back onto the wafer [A1]. The selection of a mild aqueous-organic cleaning mixture over aggressive acidic or highly alkaline solutions is directly dictated by the chemical fragility of advanced inter-metal dielectrics [A1]. Strongly alkaline environments can cause severe corrosion, deplete material density, or introduce unwanted porosity in low-k or highly doped oxide films [A1]. Therefore, the solution's ionic strength and pH must be carefully calibrated to modify surface adsorption behavior without degrading the bulk dielectric constant (Engineering Practice). Process parameter interactions are strictly controlled: increasing the cleaning fluid temperature accelerates reaction kinetics and particle desorption, but an excessive thermal budget may induce localized dielectric densification or surface dehydration, which paradoxically hinders subsequent polymer resist adhesion [P4]. At the 40nm technology node, the optical depth of focus (DOF) margin for lithography is extremely narrow, making the chemical cleanliness and micro-roughness of the post-deposition dielectric surface highly critical [P3]. Any nanoscale particle remaining on the PMD 5 layer can act as a micromask or cause local thickness variations in the spin-coated photoresist, directly translating to line edge roughness (LER) or line top spreading during the subsequent M1 trench etch [P2]. Furthermore, strict defect control at this stage is mandatory to prevent line-to-line leakage failures in tightly pitched M1 interconnects, thereby maintaining the time-dependent dielectric breakdown (TDDB) reliability of the scaled-down device [P2].