High aspect ratio resist lines are mechanically unstable and highly susceptible to pattern collapse driven by capillary forces during the post-development rinse .
In depth
The METAL 1 TRENCH - Photo step is a critical back-end-of-line (BEOL) lithography process that defines the first major lateral routing
layer in the 40nm CMOS Image Sensor flow . Positioned after the Pre Litho Cleaning and before the PMD Oxide Etch, this step patterns the inter-metal dielectric stack to prepare for copper metallization . Unlike previous contact opening steps (such as M0 Gate and S/D Contact) that define deep, narrow vertical connections to the substrate, the M1 trench step defines horizontal conductive paths . Furthermore, it is distinct from Frontside Deep Trench and STI lithography, which are front-end-of-line (FEOL) processes designed for substrate silicon isolation rather than dielectric signal routing . Because dry etching of copper is highly impractical due to the lack of volatile byproducts, the trench patterns must first be defined in the dielectric using a damascene approach, followed by metal deposition and planarization . The physical mechanism of this lithography step is governed by the Rayleigh resolution formula, where the minimum printable feature size depends on the exposure wavelength, the numerical aperture of the lens, and the process factor $k_1$ . To resolve dense 40nm node features, nanoscale immersion lithography is typically utilized to effectively reduce the wavelength and increase numerical aperture . During exposure, the aerial image contrast dictates the spatial distribution of photoacid generation within the chemically amplified resist, which in turn determines the polymer dissolution rate during the development phase (Engineering Practice). To compensate for optical distortions such as diffraction-induced line-end shortening and corner rounding, Optical Proximity Correction (OPC) is applied to the photomask to reshape the original design patterns . In via-first dual damascene integration schemes, the underlying vias must be filled with a sacrificial planarizing material, such as an organic bottom anti-reflective coating (BARC), prior to trench lithography . This planarization is essential to maintain a uniform resist thickness and keep the entire exposure field within the restricted optical depth of focus . Additionally, the anti-reflective coating suppresses standing waves generated by optical reflections from the underlying substrate, ensuring straight resist sidewall profiles (Engineering Practice). The selection of resist thickness involves a strict mechanical and chemical trade-off; a thicker resist provides sufficient masking margin for the subsequent oxide etch, but it significantly increases the aspect ratio of the developed features . High aspect ratio resist lines are mechanically unstable and highly susceptible to pattern collapse driven by capillary forces during the post-development rinse . At the 40nm node, precise control of the trench critical dimension (CD) is vital because variations directly alter the cross-sectional area of the final copper line, shifting the interconnect resistance and parasitic interlayer capacitance . Because interconnects in advanced nodes suffer heavily from size effects and electron scattering at boundaries, maximizing the process window to maintain CD uniformity is crucial for yield . If the lithography process is not tightly controlled, these geometric variations exacerbate RC delay and signal crosstalk, which are primary bottlenecks for high-speed device performance .
Risks & Challenges
[High] Pattern Collapse: High aspect ratio photoresist lines experience strong capillary forces during the drying phase of the post-development aqueous rinse, leading to structural deformation or complete collapse . This failure physically blocks the subsequent dielectric etch, causing missing trench patterns and electrical opens .
[Medium] Depth of Focus Degradation: If the underlying vias are incompletely filled by the sacrificial BARC material, local topography variations will cause the applied resist to be non-planar . This forces local regions of the wafer out of the optical focal plane during exposure, degrading aerial image contrast and causing severe critical dimension (CD) variations .
[Medium] Lithography Overlay Misalignment: Overlay errors during the M1 trench exposure shift the spatial position of the trenches relative to the pre-existing vias or contacts . This misalignment reduces the via-to-trench contact area, sharply increasing interface contact resistance and introducing asymmetric dielectric spacing that degrades RC delay predictability .
[Low] Photoresist Poisoning: Nitrogen-containing dielectric layers or underlying gap-fill materials can release basic amine contaminants that diffuse into the chemically amplified photoresist . These basic molecules neutralize the photoacid generated during exposure, locally inhibiting the resist development rate and leaving polymer scum in the intended trench openings, which subsequently blocks the plasma etch .