40nm BSI CMOS Image Sensor

In the initial stages of the 40nm BSI CMOS Image Sensor fabrication flow, defining robust global and local alignment markers is a prerequisite for achieving the stringent overlay accuracy required by subsequent lithography steps (Engineering Practice).Following nitride deposition and the alignment marker photolithography step, this Nitride Etch process acts to precisely transfer the resist pattern into the underlying silicon nitride layer [P1].The immediate next step is an Oxide Etch, which continues the pattern transfer through the thin pad oxide layer down to the silicon substrate [P1].Because the pad oxide is extremely thin, this nitride etch must be highly controlled to stop precisely on or within the oxide layer without punching through to the substrate [P1].This specific step is distinguished from other nitride removals in the flow—such as side-wall deposition and etch-back (SWEB) processes that rely on conformal film thickness rather than lithography for nanoscale definition [P2], or wet etching used for blanket stripping (Engineering Practice)—because it relies on a photoresist mask to define macro-scale topologies essential for optical alignment tool recognition (Engineering Practice).The physical operation of this step relies on Reactive Ion Etching (RIE), which combines the chemical reactivity of a low-pressure plasma with the physical directionality of ion bombardment [P4].Typically, a fluorocarbon-based gas mixture (such as CHF3 combined with O2 or CO2) is dissociated by a radio-frequency discharge into neutral reactive radicals (e [P4].g., fluorine and CFx) and positive ions [P1].The neutral fluorine radicals chemically react with the Si-N bonds to form volatile SiFx byproducts, providing the primary material removal mechanism [P4].Simultaneously, the direct current (DC) self-bias of the plasma sheath accelerates positive ions vertically into the wafer surface, imparting the physical kinetic energy required to break surface bonds and clear passivation layers at the bottom of the etched features [P4].This synergy between chemical volatilization and vertical ion momentum transfer is what enables highly anisotropic profiles, preventing the severe lateral undercutting characteristic of wet chemical etches [P3].To achieve both a high throughput and a safe landing on the thin pad oxide, a two-step RIE process scheme is generally selected [P1].The first phase operates in a high-rate, highly anisotropic regime dominated by ion bombardment to clear the bulk of the silicon nitride film rapidly, where etch selectivity is not the primary constraint [P1].As the etch front approaches the underlying oxide interface, the process transitions to a second phase featuring high Si3N4-to-SiO2 chemical selectivity [P1].This selectivity is chemically driven by the differential deposition rate of fluorocarbon polymers; the oxygen present in the underlying SiO2 film consumes the fluorocarbon precursors, whereas the nitride surface allows continuous polymer deposition that is only cleared by directional ions, or alternatively, tuning the CHF3/O2 ratio can leave a protective polymer exclusively on the oxide [P1].Adjusting parameters involves inherent trade-offs; for instance, increasing RF bias power enhances directional anisotropy and reduces RIE lag, but it simultaneously degrades the chemical selectivity to both the photoresist mask and the underlying oxide [P3].At the 40nm technology node, the precise control of critical dimensions (CD) and minimization of plasma-induced damage are paramount [P3].Any RIE lag—a phenomenon where the etch rate drops in narrower features or differing pattern densities—can lead to incomplete marker definition, severely impacting the contrast required by 40nm overlay metrology tools [P3].Furthermore, if the RIE process fails to stop reliably on the pad oxide, the energetic reactive ions will directly bombard the exposed silicon substrate during the overetch phase [P1].This plasma-induced physical damage introduces crystalline defects and stacking faults into the silicon lattice [P1].In the context of a Back-Side Illuminated (BSI) CMOS Image Sensor, such localized lattice damage is highly detrimental, as it acts as generation-recombination centers that significantly increase the dark current and degrade sensor signal-to-noise ratio (Engineering Practice).

• [High] Etch Punch-Through and Substrate Damage: Insufficient chemical selectivity during the overetch phase causes the complete consumption of the underlying pad oxide, exposing the bare silicon substrate to the plasma [P1].Energetic reactive ions bombarding the bare silicon generate crystalline dislocation defects and stacking faults, which act as severe dark current generation centers in the final image sensor device [P1].- [Medium] Profile Tapering and CD Loss: Excessive consumption of the photoresist mask or inadequate sidewall passivation during the highly selective second-step etch leads to progressive lateral etching of the nitride [P1].This loss of vertical anisotropy results in tapered sidewalls on the alignment markers, which degrades the optical contrast and edge-detection accuracy during subsequent high-resolution lithography alignments (Engineering Practice).- [Medium] RIE Lag and Incomplete Etch: Variations in local pattern density or feature size cause differential transport rates of neutral radicals and ions to the etch front, leading to RIE lag [P3].This geometric effect can result in localized patches of unetched silicon nitride at the bottom of the marker trenches, which impedes the subsequent oxide etch and causes unpredictable topography variations [P1].- [Low] Fluorocarbon Polymer Residue: Utilizing an overly rich fluorocarbon chemistry (e (Engineering Practice).g., insufficient O2 flow in a CHF3/O2 system) leads to the excessive accumulation of CFx polymer passivation on horizontal surfaces rather than just sidewalls [P1].If this hardened polymer is not completely volatilized during the subsequent ashing and strip processes, it will act as a micromask during the subsequent oxide etch, leading to severe surface roughness (Engineering Practice).