40nm BSI CMOS Image Sensor

After wafer introduction and laser marking, the silicon wafer surface is inevitably contaminated with silicon dust, organic residues, and debris [P2].The Particle Removal step is critical to prepare the surface for the subsequent Oxidation Pre-Cleaning and Oxide growth steps [A2].Any residual particulate matter acts as a micromask or creates localized stress, severely degrading the structural and electrical quality of the subsequent thermally grown oxide [T1].Since modern semiconductor device performance is heavily reliant on a near-ideal interface between the semiconductor crystal and the oxide layer, minimizing surface defects and particulate contamination at this stage is mandatory to preserve carrier surface mobility [T1].Without effective particle removal, these contaminants will be permanently embedded in the foundational layers of the BSI CMOS image sensor, causing lethal pixel defects (Engineering Practice).The removal of tightly adhered particles is primarily achieved through a combination of chemical undercutting and physical acoustic displacement (Engineering Practice).Wet-chemical approaches typically utilize oxidizing agents coupled with mild etchants to slowly dissolve the native oxide or the top few atomic layers of the substrate immediately beneath the particle, effectively breaking the van der Waals or chemical adhesive bonds [P1].This undercutting process relies on chemical reaction kinetics, where the local etch rate follows an Arrhenius relationship and is exponentially dependent on the processing temperature [A1].As the wet etchant interacts with the silicon surface, nucleophilic reactions (such as attack by OH⁻ ions) occur at the surface dangling bonds, a process whose reaction rate can vary significantly depending on the atomic packing density of the exposed crystallographic planes [P3].To prevent irreversible deep lattice dislocation or amorphization that typically occurs with high-energy physical sputtering methods, mild wet chemical etching is preferred to maintain an atomically smooth surface [P2].A wet chemical method is selected over dry physical ion bombardment because high-energy ions can cause severe lattice damage that cannot be fully annealed out at standard thermal budgets [P2].By carefully controlling the etchant solution concentration and applying precise thermal management, the chemical etching rate can be kept exceptionally low, avoiding excessive silicon substrate loss while ensuring complete particle dislodgment [A1].Furthermore, managing the etch temperature and mass transport conditions prevents the highly anisotropic etching of different crystallographic planes, which would otherwise lead to surface faceting and severe microscopic roughness [P3].Maintaining this atomic-level structural integrity and surface smoothness is paramount, as increased surface roughness directly limits the drive current capability of the final integrated circuits by enhancing surface scattering and degrading effective carrier mobility [T1].At the 40nm technology node for BSI CMOS Image Sensors, strict defectivity control is fundamentally required because even nanometer-scale particles can completely block light collection pathways or induce massive dark current leakage in the active photodiode array [T1].Furthermore, as device geometric dimensions scale down, the electrical tolerance for native oxide thickness variations and interfacial defect states diminishes significantly, leading to severe subthreshold leakage constraints [T3].Therefore, achieving near-atomic-scale precision, uniform chemical dissolution, and extreme particle cleanliness during this removal step is a foundational requirement for ensuring high quantum efficiency and device yield in advanced imaging technologies [P1].

• [High] Surface Roughening: Anisotropic wet etching caused by chemical etchants reacting at fundamentally different rates with various crystal planes (e [P3].g., slower on densely packed {111} planes compared to {100} planes) can lead to micro-faceting [P3].This resulting surface roughness enhances carrier surface scattering, which severely degrades the mobility of the inversion layer in subsequent MOS devices [T1].- [Medium] Localized Over-etching (Pitting): Variations in local thermal energy or localized prolonged chemical exposure can significantly lower the reaction activation energy barrier in specific spots, exponentially accelerating the Arrhenius-governed etch rate [A1].This excessive localized dissolution can create pits or deep depressions on the silicon surface, compromising structural planarity [P1].- [Medium] Incomplete Particle Removal: Insufficient chemical undercutting of the native oxide layer beneath the adhering particle, possibly due to depleted etchant concentration or locally depressed processing temperatures, prevents the particle from detaching [P1].This leaves physical obstructions that will disrupt the uniformity of the subsequent thermal oxide growth and introduce critical dielectric weak spots [T1].- [Low] Uncontrolled Native Oxide Re-growth: If the wafer is exposed to ambient oxygen or moisture immediately after the protective native oxide is chemically etched away, a highly non-uniform new native oxide layer can rapidly reform [P2].This uncontrolled re-oxidation can trap residual chemical contaminants or metallic impurities, interfering with the subsequent selective pre-cleaning and oxidation steps (Engineering Practice).