40nm BSI CMOS Image SensorPreview

ing pattern geometry [P3]. This Pre Litho Cleaning step acts as the critical bridge between middle-of-line (MOL) dielectric deposition and the subsequent photolithography module for Metal 1 Gate and Source/Drain (S/D) Contact Opening [P4]. Unlike earlier pre-litho cleans that operate on bare silicon or thin pad oxides, this specific step must prepare a thick bulk oxide surface to successfully receive multi-layer patternable materials, such as organic planarization layers (OPL) and anti-reflective coatings (ARC) [A3]. A pristine starting surface is mandatory because any irregularities or contaminants will be amplified during the high-aspect-ratio contact hole patterning process (Engineering Practice). Furthermore, at advanced nodes, the use of nanoscale immersion photolithography presents key problems with line edge roughness (LER), which is directly transferred into the substrate during the etching process and severely impacts final device performance [P2]. The physical and chemical mechanisms of this wet cleaning step rely on a carefully balanced oxidation and dissolution sequence [P1]. Wet-chemical mixtures, often utilizing oxidizing agents like hydrogen peroxide paired with bases or acids, dynamically modify the dielectric surface [P1]. The oxidant reacts with residual organic contaminants to form soluble complexes, enabling their complete removal from the substrate [P1]. Simultaneously, the hydrodynamics of the wet clean physically dislodge and sweep away particulate matter without inducing mechanical damage to the underlying dielectric (Engineering Practice). This process guarantees that the surface condition, which dictates the thermodynamic wetting properties, is uniformly optimized across the wafer [T1]. Proper surface termination is essential to ensure that the subsequent spin-on layers adhere without delamination or dewetting [A3]. The selection of mild, highly controlled wet chemistries is driven by the necessity to avoid undesirable surface roughening [P1]. Because the carrier mobility and contact resistance in scaled devices are highly sensitive to interface quality, atomically smooth surfaces are targeted after any surface treatment [P1]. Additionally, chemically amplified photoresists (CAR) used in conventional nanoscale lithography are extremely sensitive to chemical environments [P2]. Any residual airborne molecular contamination (AMC) or unrinsed basic ions left on the PMD surface can neutralize the photoacids generated during exposure, leading to localized pattern failures (Engineering Practice). Therefore, the cleaning chemistry is selected not only for its particle removal efficiency but also for its ability to leave a chemically neutral, structurally intact oxide surface ready for the tight resolution limits of contact layer patterning [P2]. At the 40nm technology node, the spatial density and vertical depth of the MOL local interconnects demand exceptional process control [P4]. As contact holes shrink to dimensions where resolution limits are heavily challenged, alternative lithographic technologies or highly optimized conventional methods must operate within extremely narrow process windows [P2]. Any variation in the PMD surface state can cause depth of focus (DOF) deviations across the wafer, leading to incomplete contact openings [P3]. By thoroughly standardizing the dielectric surface state immediately prior to ARC and resist application, this pre-litho clean directly suppresses the formation of blind contacts and ensures the physical integrity of the subsequent contact extension pathways [A3].