What is the 40nm BSI CMOS Image Sensor process flow?

The 40nm BSI (Backside Illuminated) CMOS Image Sensor process flow is a specialized semiconductor manufacturing sequence for high-performance image sensors. Unlike traditional front-side illuminated (FSI) architecture, BSI places the photodiode beneath the metal interconnect layers and receives light from the wafer backside, dramatically improving quantum efficiency and low-light performance. This flow contains 417 process steps and is entirely free to access.

What is the difference between BSI and FSI image sensors?

In FSI architecture, incident light must pass through the metal interconnect layers to reach the photodiode — metal lines block and reflect some light, reducing quantum efficiency. BSI flips the wafer so light enters directly from the backside into the photodiode, bypassing the metal stack. This gives BSI sensors significantly higher sensitivity at the same pixel size, making them ideal for smartphone cameras and low-light applications.

What is the role of Deep Trench Isolation (DTI) in the 40nm CIS flow?

Deep Trench Isolation (DTI) creates physical and optical barriers between adjacent pixel photodiodes in BSI CIS. The trenches are filled with low-refractive-index material, preventing photo-generated carriers from diffusing into neighboring pixels (electrical crosstalk) and blocking oblique light from crossing pixel boundaries (optical crosstalk). This is critical for maintaining image quality as pixel pitch shrinks.

What is the role of Color Filter Array (CFA) and microlens in CIS?

The Color Filter Array sits above each pixel, arranging red, green, and blue filters in a Bayer pattern (RGGB) so each pixel captures only one color. The microlens array sits above the CFA, focusing incident light onto each pixel's active area to improve light collection efficiency. In BSI architecture, the shorter optical path and absence of metal obstruction simplify CFA and microlens alignment and increase the fill factor.

What are the key modules in the 40nm CIS process flow?

Key modules include: STI (Shallow Trench Isolation), Well formation, Gate, PD (Photodiode formation), F-DTI (Frontside Deep Trench Isolation), PMD/Contact, multi-level metal interconnect (MET0-MET6), DBI (Direct Bond Interconnect — wafer bonding), backside thinning (THIN), backside passivation (BKPAS), LS Grid (Light Shield Grid), CFA (Color Filter Array), microlens (UOCL), and Bondpad. The flow spans 42 modules and 417 process steps.

40nm BSI CMOS Image Sensor - 40nm Process Flow

The 40nm BSI CMOS Image Sensor (CIS) process flow covers the complete fabrication of a backside-illuminated image sensor, from incoming wafer through color filter array and microlens formation.

Unlike front-side illuminated (FSI) sensors, the BSI architecture places the photodiode beneath the metal interconnect stack and receives light from the thinned wafer backside, achieving higher quantum efficiency and better low-light performance.

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01Pixel sensing and readout: photodiode, diffusion, and pinning3 stopsPreview

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02Backside integration: why bonding precedes thinning and passivation3 stopsPreview

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03Pixel optics: color selection, planarization, and focusing3 stopsPreview

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Key process modules include Shallow Trench Isolation (STI), photodiode formation, frontside Deep Trench Isolation (F-DTI) for pixel-to-pixel optical and electrical isolation, multi-level copper dual-damascene interconnects (MET0–MET6), Direct Bond Interconnect (DBI) for wafer-to-carrier bonding, backside thinning and passivation, Light Shield Grid for stray-light suppression, Color Filter Array (CFA) in a Bayer pattern, and microlens fabrication.

The flow spans 417 process steps across 42 specialized modules, providing detailed rationale and risk analysis for each step — grounded in academic papers, patents, and authoritative textbooks. The overview and module map are public. Sign up for a free account to read all 417 process steps. No payment is required.

The 40nm BSI CMOS Image Sensor (CIS) process flow covers the complete fabrication of a backside-illuminated image sensor, from incoming wafer through color filter array and microlens formation.

Ångström AI process guide

Understand this process in 6 key stages

Explore how the cross-section changes, understand why each step matters, and ask Ångström questions along the way.

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01Pixel sensing and readout: photodiode, diffusion, and pinning3 stopsPreview

See how the charge-collection region, readout node, and surface pinning region are established.

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02Backside integration: why bonding precedes thinning and passivation3 stopsPreview

See how support, thinning, and interface treatment establish the backside light-entry structure.

Start topic route

03Pixel optics: color selection, planarization, and focusing3 stopsPreview

See how color filters, a planar base, and microlenses work together to guide incident light.

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Step text follows your current reading access.

40nm BSI CMOS Image SensorFree after sign-in

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40nm BSI CMOS Image SensorFree after sign-in

Understand this process in 6 key stages

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Module Distribution