技术博客
深入了解半导体制造工艺的物理原理与集成逻辑
Mastering the First Via Level: Process Integration, Physics, and Advanced Node Challenges in Semiconductor Manufacturing
Introduction In modern integrated circuit (IC) manufacturing, the vertical connection of dense components is as critical as the planar placement of transistors
Deep Dive into Local Via (V0) Integration: Principles, Physics, and Advanced Node Challenges
Introduction In modern integrated circuits, the density of transistors has scaled exponentially in accordance with Moore’s Law T2. As device footprints shrink,
半导体制造中的碳化硅 (SiC)：物理特性、工艺原理与工程挑战
简介 碳化硅（SiC）是一种由硅和碳组成的化合物半导体材料，已成为现代电力电子学的基石 P1。在半导体制造业领域，传统的硅材料在极端工作条件下已接近其物理极限（工程实践）。在电动汽车和电网基础设施等应用中，对更高效率、更高功率密度和更高工作温度的需求，加速了宽禁带（WBG）材料的应用 P1, A2。SiC 展现出一系列
半导体制造中锥形轮廓刻蚀的基础：原理、机制与集成
引言 锥形轮廓刻蚀，通常被称为斜坡刻蚀或锥形刻蚀，是一种专门的等离子体刻蚀技术，旨在制造具有可控、非垂直侧壁角度的特征结构 P1, T1。虽然垂直、高度各向异性的轮廓通常是集成电路保持高间距密度（pitch density）的黄金标准，但某些结构需要正斜率以利于后续加工 T1, P3。在半导体制造中，创建锥形斜坡对于确
Dual Gate Oxide Engineering: Physical Principles, Integration Challenges, and Node Evolution in Advanced CMOS Manufacturing
Introduction In modern microelectronics, the relentless pursuit of device scaling has driven complementary metal-oxide-semiconductor (CMOS) technology to remark
Demystifying Contact Hole Etch: Process Physics, Integration Principles, and Advanced Node Challenges
Introduction The fabrication of modern integrated circuits is divided into distinct manufacturing phases, where the transition between the active device layer a
Guide to Salicide Block (SAB): Principles, Process Integration, and Advanced Node Evolution
Introduction The self-aligned silicide (salicide) process has been a cornerstone of silicon technology since its development in the early 1990s T1. The primary
Principles and Integration of Self-Aligned Silicide (Salicide) in Advanced Semiconductor Manufacturing
Introduction Self-aligned silicide (salicide) technology has served as a foundational building block for modern high-speed complementary metal-oxide-semiconduct
Wet Chemical Cleaning in BEOL: The Science and Engineering of EKC Post-Etch Residue Removal
1. Introduction In modern ultra-large-scale integration (ULSI) semiconductor manufacturing, defining features at sub-nanometer scales requires an intricate danc
Principles of Self-Aligned Contact Oxide: Physics, Process Integration, and Advanced Node Scaling
Introduction In the early era of planar complementary metal-oxide-semiconductor (CMOS) technology, contact placement was primarily governed by lithographic regi
先进半导体制造中突破性刻蚀（Break-Through Etch）的原理与集成
引言 在先进半导体制造领域，实现亚纳米级的结构精度需要对每一个界面和薄膜表面进行绝对控制 A2。在基于等离子体的干法刻蚀工艺中，最关键但常被忽视的阶段之一是初始步骤：穿通刻蚀（break-through etch），也称为突破刻蚀、BT刻蚀或初始刻蚀 T1。 在对主要目标材料（如多晶硅、金属或先进电介质）进行图形化之前
栅极互连指南：物理原理、工艺集成与纳米级演进
引言 在现代半导体制造中，栅极互连代表了有源晶体管开关元件与上层金属化布线层之间的关键物理及电气桥梁 T1。该接口负责向栅极提供电压激励，通过调节晶体管沟道的静电势来切换器件的导通与关断状态 T3。从历史上看，为了降低电气短路的风险，栅极接触点通常被设置在远离有源沟道区域的位置；然而，随着器件尺寸的缩小，这种布局策略成