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Process lessons

Transistors and isolation

Spacer etch-back: coating, removal and retention — After step 107 · retained gate spacersGateSiliconSpacer
Spacer etch-back · 28nm

How do spacers form beside the gate?

See horizontal film removed while sidewall film remains.

See how spacers form
STI: trench etching, liner oxidation and dielectric fill — Step 18 · oxide fillSiDielectric fillLiner
STI · 28nm

How are isolation trenches formed in silicon?

Follow the mask opening, silicon etch and oxide fill.

Follow trench formation
FCVD: STI liner, dielectric fill and CMP — Step 37 · oxide CMPSiDielectric fillLiner
FCVD · 14nm

What do the liner, fill and CMP each do?

Protect the interface, fill the trench, then clear the surface.

Compare the three operations
Replacement metal gates: high-k, dummy gate and final electrode — Step 167 · final gate CMPMetal electrodeSi
Replacement gates · 28nm

How does the metal gate replace the dummy gate?

Follow dummy removal, cavity formation and the final electrode.

Follow dummy-gate replacement

Contacts and interconnects

Copper dual damascene: vias, trenches and CMP — Step 224 · after copper CMPM2V1M1Dielectric
Copper · 28nm

How are copper interconnects formed?

Follow copper fill and CMP to see how separate lines form.

Explore copper fill and CMP
Self-aligned contacts: hardmask, opening and tungsten fill — Step 194 · CMP after tungsten fillTungsten fillDielectricTerminal simplified
SAC · 14nm

How is a tungsten contact formed?

Follow the hard mask, opening and tungsten CMP.

Follow contact formation
LELE: two exposures and pattern transfer — Step 319 · integrated opening etchE1 retainedE2Underlying material
LELE · 7nm

Where is the first pattern during the second exposure?

See how the first pattern is retained and both sets become openings.

Follow the two pattern sets

Image sensors

Pixel junctions: photodiode, FD and surface pinning — Step 99 · surface p pinningPD (n)FD (n)TGp-type pinningp-type silicon
Pixel junctions · 40nm

What do PD, FD and the pinning region do?

Locate the regions for charge collection, voltage sensing and surface control.

Explore the three pixel regions
Backside integration: bonding, thinning and passivation — Step 307 · backside AlO depositionCISBackside passivationFrontside interconnectOpposing wafer
Backside integration · 40nm

Why bond the wafer before backside thinning?

Follow support, silicon thinning and backside treatment.

Follow bonding, thinning and passivation
Pixel optics: color filters, a planar base and microlenses — Step 378 · microlens reflowMicrolensColor filters
Pixel optics · 40nm

What do color filters and microlenses each do?

Follow filter patterns, a planar base and lens curvature.

Explore the pixel optical stack

Node lessons

Explore process dependencies, materials and routes. Included with the corresponding node.

28nm · Node lessonChecking access…

Why does the STI sequence follow this order?

Examine the sequence of trench etching, stripping, cleaning, liner oxidation and fill.

14nm · Node lessonChecking access…

How do SOG, SOC and FCVD differ?

Compare SOG, SOC and FCVD by material class, film formation method and post-deposition treatment.

28nm · Node lessonChecking access…

Via first or trench first: what does the next step receive?

Compare via-first and trench-first routes, including temporary fill and subsequent metallization.