Why bond the wafer before backside thinning?
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Bond for support
Bonded side: bottom, near frontside interconnect. Backside to be thinned and passivated: top. The view stays fixed.
Backside-illuminated (BSI) image sensors thin the silicon substrate to a few micrometers so incident light enters the photodiode directly without frontside metal obstruction. Follow wafer bonding, backside silicon thinning/CMP1, and high-k Al₂O₃ passivation to see how mechanical support, subsurface damage removal, and field-effect passivation work together.
CIS/ISP Wafer TC Bond aligns and joins the sensor wafer to an opposing ISP wafer, providing rigid mechanical support for subsequent extreme backside thinning and 3D integration. Frontside devices and interconnect sit near the lower bonded interface.
- Mechanism
- Across a copper–dielectric hybrid bond interface, dielectric regions and copper pads serve distinct roles: activated dielectric surfaces establish wafer-scale mechanical attachment and isolation, while opposing copper pads—governed by initial pad recess and vacancy evolution—interdiffuse during annealing to form vertical electrical continuity.
- Process integration
- Silicon thinned to a few micrometers cannot withstand grinding shear stress without a bonded carrier wafer; however, mechanical stack attachment does not automatically certify electrical continuity at every copper pad—mechanical bonding, copper conduction, and dielectric isolation require separate structural and electrical verification.
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Remove silicon from the backside
Supported by the lower bonded wafer, bulk silicon is removed from the top backside (via grinding and CIS Backside Si CMP1), reducing remaining silicon thickness and removing subsurface grinding damage. Frontside interconnect stays near the lower bonded side; the view has not flipped.
- Mechanism
- Coarse mechanical grinding leaves severe subsurface damage, work-hardened zones, and total thickness variation (TTV); subsequent Backside Si CMP1 uses alkaline slurry chemistry to rapidly oxidize and hydrate exposed silicon into a mechanically softened reaction layer that colloidal silica abrasives shear away.
- Process integration
- Thinning eliminates parasitic bulk absorption and prepares a smooth, damage-free surface for final CMP2 thickness targeting; however, slurry byproduct agglomeration scratches or unpassivated backside dangling bonds will directly degrade pixel dark current.
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Treat the thinned surface
On the thinned and conditioned silicon backside, HKD/AR1 AlO deposition forms an aluminum oxide (Al₂O₃) film that provides both electrical surface passivation and the first anti-reflective (AR1) optical layer. The diagram locates this treatment; electrical and optical performance are confirmed by testing.
- Mechanism
- The Al₂O₃ layer suppresses dark current through dual chemical and field-effect passivation: initial ALD cycles satisfy silicon dangling bonds to lower Shockley-Read-Hall (SRH) interface trap density, while intrinsic negative fixed charges in Al₂O₃ induce a backside hole accumulation layer that repels electrons away from the surface.
- Process integration
- This Al₂O₃ film also serves as the foundational optical layer (AR1) for subsequent TaO anti-reflective stacks; if trapped hydrogen or moisture outgasses during downstream thermal steps to cause blistering or delamination, both dark-current suppression and optical transmittance degrade.
Key ideas
Backside-illuminated (BSI) image sensors invert the spatial order of optical path and metal routing to eliminate frontside BEOL shadowing of incident photons. Because thinning an unsupported wafer to a few micrometers would cause severe warpage or fracture and frontside Cu interconnect is already present, this Flow first flips and bonds the completed CIS wafer face-to-face onto the ISP wafer at step 290, then performs backside silicon CMP at step 295 to remove grinding subsurface micro-cracks and bring the photodiodes near the illuminated surface, and finally deposits a low-temperature negative-fixed-charge Al₂O₃ film at step 307 for field-effect hole-accumulation passivation and antireflective matching.
View the process comparison table
| Process dimension | Core mechanism and selectivity | Window mismatch risk and verification boundary |
|---|---|---|
| Wafer bonding (step 290) | Plasma-activated hydrophilic silanol groups condense into covalent Si–O–Si bonds with thermocompression interdiffusion to lock the 3D stack. | Particle-induced bond voids cause thin-silicon blistering and delamination during thinning; bond integrity requires acoustic microscopy (C-SAM). |
| Backside Si CMP (step 295) | Alkaline slurry hydroxyl attack weakens Si–Si bonds for gentle abrasive shear, removing subsurface micro-cracks left by coarse back-grinding. | Total thickness variation (TTV) drift skews optical absorption path and spectral response across the wafer; frontside device identity remains unchanged. |
| Backside Al₂O₃ passivation (step 307) | High-density negative fixed charge induces a backside hole accumulation layer that repels thermally generated interface electrons while aiding AR matching. | Degraded negative fixed-charge density spikes backside dark current and white pixels; a film schematic cannot verify quantum efficiency (QE) or dark current. |
About this schematic
Uses a fixed viewing orientation with simplified bands for frontside interconnect and the bond interface without detailing micro-bumps or hybrid-bond pads. Steps 291–294 bond anneal, coarse back-grinding, and wet stress relief, as well as steps 296–306 fine CMP2 and backside surface conditioning, are omitted; no C-SAM or electro-optical test data are shown.