What do the liner, fill and CMP each do?
1 / 3
Deposit the liner
The thin gold layer is the conformal STI liner along the trench walls; teal marks the FCVD fill dielectric. Locate the thin liner boundary on the silicon wall first, then track the trench interior and field overburden.
High-aspect-ratio inter-fin trenches in 14nm FinFETs are prone to top pinch-off under conventional conformal deposition. Follow liner deposition, bottom-up flowable CVD (FCVD) gap fill, and SiN-stop CMP to separate interface buffering, capillary gap fill, post-treatment densification, and planarization.
An ultrathin conformal STI liner is deposited along the exposed trench sidewalls and floor. It follows the trench contour to establish an interface barrier and stress buffer while leaving most of the trench interior open for bulk dielectric fill.
- Mechanism
- Surface-reaction-controlled conformal deposition achieves spatially uniform coverage across 3D fin sidewalls and trench corners, passivating surface active sites and blocking oxidant diffusion into the silicon fin during subsequent oxidative curing.
- Process integration
- Liner continuity and intrinsic stress directly protect fin width (W_fin) fidelity and channel carrier mobility, but its role is strictly interfacial—void-free volume filling is handed off to downstream FCVD.
2 / 3
Fill the trench
Flowable chemical vapor deposition (FCVD) introduces flowable silicon-containing oligomers over the liner, filling the narrow trench interior and forming a continuous field overburden. The trench volume is now occupied, while excess dielectric remains across the top surface.
- Mechanism
- Gas-phase radicals and precursors condense on the cooled substrate into low-viscosity liquid-like oligomers (containing Si–H and Si–NH linkages) that flow bottom-up into the trench floor under capillary wetting and surface tension, bypassing the top pinch-off of conformal vapor growth.
- Process integration
- As-deposited FCVD film is porous and rich in H/N species; it requires oxidative steam annealing and thermal curing to cross-link oligomers into a dense SiO₂ network (accompanied by volume shrinkage), while field overburden awaits CMP removal.
3 / 3
Clear the surface
SiO₂ CMP to the SiN stop layer removes excess field oxide outside the trench and stops on the active-area silicon nitride pad, retaining only the in-trench isolation dielectric and establishing a globally planar surface. Conversion and densification are assessed through post-treatment and material characterization.
- Mechanism
- Slurry chemistry hydrolyzes and softens surface Si–O bonds while abrasive nanoparticles under pad asperity contact pressure (following the Preston relation) shear away the softened oxide; upon reaching the SiN pad, high oxide-to-nitride selectivity and surface passivation arrest removal.
- Process integration
- CMP delivers geometric coplanarity and a defined isolation height reference for downstream hard-mask deposition and lithography depth-of-focus (DOF); however, surface planarity cannot substitute for independent characterization of network conversion and densification.
Key ideas
Tight-pitch deep trenches in 14nm FinFETs push conventional conformal CVD past its sidewall pinch-off limit, motivating a decoupled 'conformal liner + flowable fill + conversion/densification + selective CMP' architecture: step 34 STI liner builds a chemical barrier and shrinkage-stress buffer along the fin sidewalls; step 35 FCVD leverages capillary surface tension of liquid-like oligomers for bottom-up void-free fill, which must then be cured and annealed to outgas H/N species and cross-link into a dense Si–O–Si network; step 37 CMP uses high-selectivity CeO₂ slurry to clear field overburden and stop precisely on the fin-top SiN hardmask. Surface planarity and internal bonding density are therefore independent physical dimensions.
View the process comparison table
| Process dimension | Core mechanism and selectivity | Window mismatch risk and verification boundary |
|---|---|---|
| STI liner deposition (step 34) | Self-limiting surface reactions conformally coat an ultrathin dielectric liner on fin sidewalls and trench bottoms to isolate silicon and buffer shrinkage stress. | Poor step coverage exposes silicon fins to parasitic oxidation during anneals or induces fin bending under tensile shrinkage stress. |
| FCVD dielectric fill (step 35) | Gas-phase radicals condense low-molecular-weight silicon oligomers that flow into narrow trench bottoms via capillary wetting, eliminating pinch-off voids. | As-filled film is rich in Si–H/N–H bonds with a loose network; geometric fill does not establish HF wet-etch resistance or dielectric breakdown strength. |
| Dielectric conversion and densification | Curing and steam/thermal annealing drive H/N outgassing and cross-link the 3D Si–O–Si backbone into dense silicon dioxide. | Incomplete conversion causes non-uniform recess during CMP and Fin Reveal wet etch; actual cross-linking and density require FTIR/XRR characterization. |
| Oxide CMP (step 37) | Removes field oxide overburden, retains trench dielectric and planarizes the surface; high-selectivity slurry passivates exposed SiN for self-stopping. | Overpolishing causes wide-trench dishing or fin-top SiN erosion, directly destabilizing effective fin height (H_fin) after Fin Reveal. |
About this schematic
Omits step 36 pre-CMP high-density oxide cap deposition and unnumbered UV-cure / steam-densification anneal sub-steps, and simplifies the scale of the fin-top SiN stop layer and ultrathin liner. Actual conversion degree, shrinkage stress, and wet-etch rate ratio require process specifications and material characterization.