How are copper interconnects formed?
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Etch vias and trenches
M1 at the bottom is the completed lower copper line, V1 in the middle is the vertical interlevel via, and M2 at the top is the upper wiring trench. Brown marks copper conductor; start by inspecting the connected dielectric cavity before plating.
Because copper lacks volatile halide byproducts for direct reactive-ion etching at tight pitches, interconnects use dual-damascene integration. Follow low-k cavity etching, electrochemical plating (ECP) superfill, and Cu CMP to see how vias and trenches are etched, filled, and isolated.
V1M2 Etch patterns the low-k SiOCH interlayer dielectric to form a combined cavity consisting of the V1 via reaching M1 below and the M2 wiring trench above. At this stage the structure is an open dielectric cavity; barrier and copper seed deposition precede copper fill.
- Mechanism
- Fluorocarbon plasma assisted by directional ion bombardment cleaves Si–O bonds into volatile silicon fluorides while sidewall polymer passivation maintains vertical profiles; ion and radical exposure must be bounded to prevent –CH₃ depletion and k-value degradation in porous low-k sidewalls.
- Process integration
- After cavity etching and post-etch clean, a conformal TaN/Ta diffusion barrier (blocking Cu⁺ drift into low-k dielectric) and a continuous PVD copper seed layer must be deposited to provide a low-resistance cathode path for electroplating.
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Electroplate copper
Copper electrochemical plating (ECP) reduces copper ions onto the continuous seed layer, filling the V1 via and M2 trench bottom-up while leaving a continuous copper overburden across the field surface. This excess copper bridges neighboring lines and must be removed.
- Mechanism
- Plating electrolytes rely on differential transport and adsorption of organic additives for bottom-up superfill: bulky suppressors (e.g., PEG) adsorb on field and top corners to inhibit growth, while small-molecule accelerators (e.g., SPS) concentrate at the shrinking via/trench bottom (curvature-enhanced accelerator coverage, CEAC), driving rapid bottom-up fill without central seams.
- Process integration
- Bottom-up superfill inevitably produces topography mounding over dense features alongside a wafer-wide conductive overburden; subsequent thermal annealing (for grain growth) and Cu CMP are required to remove the surface shorting layer.
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Separate the lines with CMP
M2 Cu CMP polishes away the excess copper and conductive barrier over the field dielectric, retaining copper solely inside the V1 via and M2 trench to separate neighboring lines. Fill integrity, barrier condition and connection resistance require their own tests.
- Mechanism
- Cu CMP balances chemical oxidation, passivation, and mechanical abrasion: slurry oxidizers (H₂O₂) convert surface Cu into Cu₂O/CuO, corrosion inhibitors (such as BTA) passivate recessed regions, and pad asperities with colloidal abrasives selectively shear away high-point films for complexing dissolution.
- Process integration
- Excessive overpolish causes copper dishing in wide lines and dielectric erosion in dense arrays, shrinking cross-sectional area and degrading electromigration (EM) lifetime; top-surface planarity cannot replace interface characterization and electrical testing.
Key ideas
Because copper lacks volatile halide etch products, BEOL interconnect uses an inverted dual-damascene architecture: etching connected V1 via and M2 trench cavities into the low-k ILD, depositing a TaN/Ta diffusion barrier and continuous PVD copper seed, executing suppressor-accelerator-leveler bottom-up superfilling electroplating, and finishing with grain-growth anneal and multi-step CMP to clear field metal and isolate M2 lines. Because CMP acts only on top-surface topography, any earlier seed discontinuity, unreduced bottom CuOₓ, or plating seam void remains buried inside the via and requires TEM/EELS interface characterization and electrical testing.
View the process comparison table
| Process dimension | Core mechanism and selectivity | Window mismatch risk and verification boundary |
|---|---|---|
| Diffusion barrier (TaN/Ta) | Dense amorphous TaN blocks thermal and field-assisted Cu⁺ drift into low-k ILD, while inner α-Ta improves wetting and adhesion for the copper seed. | Sidewall discontinuity triggers time-dependent dielectric breakdown (TDDB); overly thick bottom barrier directly increases V1 series resistance. |
| Copper seed (PVD Cu seed) | Establishes a low-sheet-resistance continuous cathode equipotential surface across the cavity and provides oriented nucleation sites for plating. | Via-mouth overhang or lower-sidewall discontinuity interrupts local Faradaic current, creating bottom plating voids that CMP cannot repair. |
| Superfilling Cu electroplating (step 222) | Large PEG molecules suppress field deposition while small SPS molecules concentrate at the shrinking via bottom to accelerate Cu²⁺ reduction for bottom-up fill. | Additive imbalance causes center-seam voids or top mounding; a cross-section schematic cannot prove an oxide-free or void-free V1/M1 bottom interface. |
| Multi-step copper CMP (step 224) | Oxidizer, complexing agent, and BTA inhibitor clear field copper overburden before a selective barrier slurry removes field TaN/Ta and stops on low-k ILD. | Underpolishing leaves field metal bridges that short adjacent M2 lines; overpolishing induces wide-line copper dishing and dense-array dielectric erosion. |
About this schematic
Compares steps 218, 222, and 224 while omitting steps 219–221 post-etch polymer wet clean, degas/pre-clean oxide reduction, PVD TaN/Ta barrier and Cu seed deposition, and step 223 post-plating anneal; nanoscale barrier/seed films are not drawn to scale. The depicted fill profile does not constitute measured proof of void-free fill or qualified contact resistance.