How does the metal gate replace the dummy gate?
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Form the gate dielectric first
Purple marks the early-formed HfO₂ high-k gate dielectric, the central opening is the replacement gate cavity after dummy silicon removal, and brown marks the final metal electrode retained in the cavity. The first view shows the dielectric only; dummy silicon gate formation is simplified.
As conventional SiO₂/polysilicon gates scale toward nanometer equivalent oxide thickness (EOT), quantum tunneling leakage surges while poly depletion and Fermi-level pinning degrade threshold voltage (V_t) control. Follow this 28nm High-k First / Gate-Last flow through ALD HfO₂ deposition, dry-plus-wet dummy silicon removal, and replacement metal-gate CMP.
In this 28nm flow, after surface pre-conditioning and nitridation, atomic layer deposition (ALD) forms the insulating high-k HfO₂ gate dielectric early in the gate module. A later dummy silicon gate preserves the gate position during intermediate processing; the final metal electrode is not yet present.
- Mechanism
- ALD relies on sequential, self-limiting surface half-reactions between precursor and oxidizer pulses for monolayer thickness control; high-permittivity HfO₂ achieves a small equivalent oxide thickness (EOT) and strong channel electrostatic control with a physically thicker film that suppresses direct tunneling leakage.
- Process integration
- In this 28nm High-k First / Gate-Last sequence, the high-k dielectric forms before source/drain processing while final work-function and fill metals are deferred; the dummy silicon placeholder absorbs the source/drain activation thermal budget without causing metal interdiffusion or work-function drift.
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Remove the dummy silicon gate
After source/drain activation and ILD0 deposition/CMP expose the dummy polysilicon top, sequential dry and wet removal hollow out the dummy gate. The cavity illustrates this stage; dry opening, wet clearing, cleaning, and interface treatment precede replacement metal-gate processing.
- Mechanism
- Dummy polysilicon removal combines directional dry etching with isotropic wet etching: dry etching first opens the laterally confined bulk polysilicon to establish an accessible reaction front, after which selective wet chemistry reaches plasma-shadowed corners without ion bombardment damage to clear residual polysilicon stringers.
- Process integration
- Coupling dry bulk opening with damage-free wet clearing converts the trench into a chemically clean cavity while preserving the underlying dielectric interface; any unremoved silicon stringers in corners would block subsequent work-function metal nucleation and shift V_t.
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Retain metal in the gate cavity
After work-function and fill metal deposition inside the cavity, Metal Gate CMP (MG CMP) clears excess surface conductor and conductive liners from the field and retains the final electrode inside the cavity. Compare the early view: the high-k dielectric formed first; the final metal electrode was added later.
- Mechanism
- The metal electrode eliminates polysilicon depletion capacitance and Fermi-level pinning; MG CMP combines slurry oxidation/complexation with abrasive contact to clear the multimetal overburden while balancing electrochemical potentials across dissimilar metals to prevent galvanic corrosion and gate-top dishing.
- Process integration
- MG CMP sets the final gate height and planarity relative to surrounding interlayer dielectric for downstream contact patterning, whereas lateral channel length (L_g) and sidewall boundaries were already inherited from early dummy-gate patterning and spacers rather than redefined by CMP.
Key ideas
High-k metal gate (HKMG) combines high-permittivity HfO₂ for equivalent oxide thickness (EOT) scaling with metal electrodes to eliminate poly depletion and Fermi-level pinning. Because exposing final work-function metals to source/drain spike anneals causes oxygen-vacancy drift and threshold-voltage (V_th) shift, this 28nm planar Flow uses a High-k-First / Gate-Last architecture: step 45 deposits planar ALD HfO₂ beneath a sacrificial polysilicon gate that endures spacer, S/D anneal, and ILD0 CMP open steps; steps 155–156 use a 'dry bulk etch + selective wet soft-landing' sequence to extract the dummy poly without punching through the bottom high-k film; work-function and fill metals are then deposited and planarized by MG CMP at step 167.
View the process comparison table
| Process dimension | Core mechanism and selectivity | Window mismatch risk and verification boundary |
|---|---|---|
| Early high-k deposition (step 45) | Self-limiting ALD half-reactions grow high-permittivity HfO₂ monolayer-by-monolayer on the interfacial oxide (IL), lowering EOT at greater physical thickness. | Because this Flow is High-k-First, HfO₂ lies flat at the gate base rather than wrapping U-shaped up cavity sidewalls; IL regrowth during anneals raises EOT. |
| Dry/wet dummy removal (steps 155–156) | Step 155 low-bias plasma rapidly thins bulk polysilicon, and step 156 switches to ultra-selective wet chemistry to clear residual silicon on the bottom high-k. | Dry over-etch damages the ultrathin high-k dielectric, while incomplete wet etch leaves corner poly stringers that block work-function metal seating. |
| Final metal-gate CMP (step 167) | Clears continuous work-function and fill metals from field ILD0, isolating conductive electrodes within their respective gate trenches. | Overpolishing induces gate-height loss that shifts contact etch windows and gate resistance; cross-sections do not verify interface states or V_th. |
About this schematic
The early view highlights the high-k dielectric baseline without detailing dummy polysilicon deposition and gate etch; later views simplify capping layers, dual N/P work-function metals, wetting layers, and bulk fill metal into a single electrode block. Spacer, S/D anneal, and ILD0 planarization steps lie between 45 and 155, and step 155 dry etch must be followed by step 156 wet removal and cleaning.