How do spacers form beside the gate?
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Start with a continuous film
Dark blue is the gate, light gray is the silicon substrate, and orange is the silicon nitride film from a single conformal deposition. Compare the vertical projection along the gate sidewalls against the horizontal gate top and source/drain flats.
Gate sidewall spacers establish a nanometer-scale self-aligned offset between heavy source/drain (S/D) implants and the gate channel without an extra lithography mask. Follow conformal dielectric deposition and maskless anisotropic etch-back to see how surface orientation and directional ions convert a continuous nitride coating into vertical sidewall spacers.
After gate patterning and lightly doped source/drain extension (LDD) implantation, conformal deposition coats the gate top, vertical gate sidewalls, and surrounding flat surfaces with a continuous silicon nitride film. The film is still continuous, before separate sidewall spacers have formed.
- Mechanism
- Surface-reaction-controlled conformal deposition grows at a uniform normal thickness on both horizontal and vertical surfaces; however, geometric projection along the vertical axis (Z-axis) gives the film hugging the vertical gate sidewalls a much greater vertical height than the single film thickness on flat horizontal surfaces.
- Process integration
- At this point the continuous dielectric blankets the entire wafer and cannot yet mask selective source/drain processing, but its initial conformal thickness directly sets the target lateral spacer critical dimension (Spacer CD) after etch-back.
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Etch back the horizontal film
Spacer2 Etch performs a maskless anisotropic dry etch-back: directional etching removes nitride faster from the horizontal gate top and surrounding flat surfaces while leaving film along the vertical gate sidewalls. Compare the previous diagram to see how the same coating evolves on differently oriented surfaces.
- Mechanism
- In hydrofluorocarbon plasma (CH₃F/CH₂F₂/O₂), vertically accelerated ions deliver normal momentum to horizontal surfaces, clearing surface polymer and activating Si–N bond cleavage; along vertical gate sidewalls, ions strike at grazing incidence without normal momentum transfer, allowing CHₓFᵧ passivation to shield the sidewall from lateral radical attack.
- Process integration
- As horizontal nitride clears, optical emission spectroscopy (OES) endpoint detection and a high-selectivity soft-landing over-etch are required to clear horizontal surfaces without punching through the underlying oxide liner or causing silicon substrate recess.
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Leave spacers beside the gate
Once the horizontal film is cleared, the dielectric structures remaining beside the left and right vertical gate walls form self-aligned spacers. They follow the gate edge and set a precise lateral offset between the gate channel and subsequent heavy source/drain processing.
- Mechanism
- By combining vertical thickness projection from conformal deposition with directional vertical ion etch-back, spacer formation self-aligns to the gate edge without a lithography mask, eliminating overlay error.
- Process integration
- Final spacer width directly governs transistor electrical trade-offs: excessive etch-back thinning (CD loss) lets heavy source/drain dopants encroach under the gate, increasing overlap capacitance (C_gd) and short-channel degradation (DIBL), whereas unetched bottom footing increases series resistance.
Key ideas
Sidewall spacers establish nanometer-accurate self-aligned offset boundaries beside the gate without a dedicated lithography mask, relying on the geometric projection path difference between conformal deposition and maskless anisotropic etch-back: earlier conformal deposition coats the gate top, sidewalls, and source/drain field with uniform normal film thickness, but viewed vertically the film along the gate sidewall has a cumulative height equal to gate height plus film thickness—far exceeding the single film thickness on horizontal surfaces. When vertically collimated fluorocarbon ions bombard the wafer at step 107, the horizontal gate-top and field films clear first while the tall vertical sidewall columns remain as symmetric spacers that offset deep S/D implants, prevent salicide bridging, and bound the later RMG cavity.
View the process comparison table
| Process dimension | Core mechanism and selectivity | Window mismatch risk and verification boundary |
|---|---|---|
| Before etch-back: conformal coating | Prior thermal/ALD/PECVD deposition coats uniform normal thickness across gate top, sidewalls, and field, creating a tall vertical projection along sidewalls. | Initial film thickness and step coverage set the upper bound of final spacer width; while continuous, the film blocks source/drain silicidation and implants. |
| Within step 107: anisotropic etch-back | Sheath-accelerated vertical ions break bonds rapidly on horizontal surfaces, while vertical walls experience grazing incidence and CHₓFᵧ passivation. | Insufficient anisotropy laterally thins the spacer and shortens L_eff; over-etch punching through the bottom oxide liner causes source/drain silicon recess. |
| After step 107: retained self-aligned spacer | As horizontal surfaces clear, the remaining vertical columns lock beside the gate without a mask, inheriting gate position to offset S/D and salicide. | Top shoulder faceting erodes later RMG and SAC anti-bridging margin; an ideal schematic outline does not prove zero plasma damage on exposed silicon. |