What do PD, FD and the pinning region do?
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Form the PD-related region
PD is the photodiode on the left, TG is the central transfer gate, and FD is the floating diffusion node on the right. The diagrams show wafer fabrication implant stages.
At the heart of a CMOS image sensor (CIS) pixel is the pinned photodiode (PPD). Follow deep n-type photodiode well implantation, heavy n+ floating diffusion (FD) implantation, and shallow p+ surface pinning implantation to see why PD and FD—though both containing n-type silicon—serve distinct physical roles in fully depleted charge storage and charge-to-voltage conversion.
N Photocathode IIPX uses high-energy ion implantation to introduce a controlled deep n-type core inside the p-type epitaxial layer, forming the primary photodiode (PD) potential well that collects and stores photogenerated charge.
- Mechanism
- Lighter phosphorus (P) ions penetrate the silicon lattice to achieve a deeper projected range (R_p) than heavier arsenic (As) at comparable implant energies, forming a wide-depletion p-n junction within p-epi whose built-in electric field separates photogenerated electron-hole pairs and collects electrons.
- Process integration
- The PD n-type dose must be tightly bounded so the region fully depletes to a stable pinning potential (V_pin) after charge transfer; excessive dose leaves undepleted residual electrons that cause severe image lag and nonlinear transfer.
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Form the FD-related region
After transfer gate (TG) and sidewall spacer formation, NMOS S/D, FD IIP implants a high-dose n+ region on the opposite side of TG to form the floating diffusion (FD). During operation, FD receives transferred charge for charge-to-voltage conversion; although both PD and FD include n-type regions, their roles depend on structure and potentials.
- Mechanism
- High-dose shallow implantation creates the heavily doped n+ junction required for low-resistance contact and charge sensing; implanting after spacer formation offsets the n+ peak laterally from the TG edge, limiting gate overlap capacitance (C_ov) and avoiding extreme junction electric fields that trigger band-to-band tunneling (BTBT) dark current.
- Process integration
- PD and FD serve distinct electrical roles: PD is a lightly doped, fully depleted buried storage well, whereas FD is a heavily doped sense node wired to the source-follower gate whose conversion gain (CG = q / C_FD) demands minimal parasitic capacitance and zero metal-impurity white-pixel defects.
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Form the surface pinning region
P-Pinning IIP introduces a shallow p-type pinning region near the PD surface, establishing the p⁺-n-p buried photodiode potential boundary. These three views follow fabrication order; exposure, transfer and readout use a separate operating sequence in the completed device.
- Mechanism
- The top silicon–oxide interface hosts dangling-bond generation-recombination centers; the shallow p+ pinning layer floods the surface with majority holes to passivate interface traps, pins surface potential to the substrate, and pushes the potential maximum into the silicon bulk to suppress surface dark current.
- Process integration
- Fabrication order (deep PD implant, gate/spacer and n+ FD implant, then shallow p+ pinning) builds the doping profile, whereas completed device operation follows the electrical sequence: PD photoelectron integration → TG-gated charge transfer via self-induced drift and fringing fields → FD voltage readout.
Key ideas
A 40nm BSI pinned photodiode (PPD) builds a 3D electrostatic potential corridor for lag-free readout through staged ion implants: step 54 medium-energy phosphorus implant forms the deep n-type PD collection well; after transfer-gate (TG) patterning, step 93 high-dose n⁺ implant self-aligns the floating diffusion (FD) and pixel transistor source/drains; step 99 shallow low-energy p⁺ implant adds the surface pinning layer, completing a P⁺–N–P double junction with a pinned depletion potential (V_pin). One must strictly separate the wafer fabrication sequence (steps 54→93→99) from post-fabrication operating readout timing (integration → TG transfer pulse → FD correlated double sampling).
View the process comparison table
| Process dimension | Core mechanism and selectivity | Window mismatch risk and verification boundary |
|---|---|---|
| PD collection region (step 54) | Medium-energy donor implant before gate formation creates a deep n-type potential well that collects and stores photogenerated electrons. | Excess dose raises pinned depletion voltage (V_pin) beyond TG transfer capability, causing lag; schematic blocks do not show true full-well capacity (FWC). |
| FD readout node (step 93) | High-dose n⁺ self-aligned implant opposite the TG forms a low-resistance ohmic contact and low C_FD for high-conversion-gain charge-to-voltage sensing. | Implant damage or metal contamination elevates FD junction leakage and reset noise; though n-type like PD, its doping level and circuit role are distinct. |
| Surface p⁺ pinning (step 99) | Shallow acceptor implant forms a P⁺–N–P double junction, pushing the potential maximum away from the Si/SiO₂ interface and suppressing surface dark current. | Lateral p⁺ encroachment into the TG edge creates a transfer potential barrier/pocket; image lag and white-pixel defects require electro-optical testing. |
About this schematic
The schematic does not depict actual Gaussian doping profiles, true junction-depth scale, or 3D electrostatic equipotential contours. Gate oxidation, polysilicon transfer-gate (TG) etching, and offset spacer steps between 54 and 93 are omitted; TG in later views marks spatial boundaries rather than its full fabrication, and no operating electron-transfer trajectories are shown.