How is a tungsten contact formed?
1 / 3
Deposit the hard mask
The dark top film is the silicon nitride hard mask, light gray below is the interlayer dielectric (ILD), and brown marks the tungsten retained in the contact opening. Gate caps and spacers are simplified to highlight hard-mask transfer, dielectric opening, and field tungsten clearing.
At sub-20nm tight gate pitches, source/drain contact openings approach the inter-gate spacing, where lithography overlay error alone would short contacts to the gate. Follow hard-mask deposition, high-selectivity self-aligned contact (SAC) dielectric etching, and tungsten CMP to see how etch selectivity decouples contact placement from overlay limits.
PECVD SiN hard-mask deposition forms a continuous, uniform silicon nitride film above the oxide hard mask and interlayer dielectric (ILD). It is still continuous with no contact opening yet, preparing for deep contact pattern transfer.
- Mechanism
- Plasma-enhanced CVD (PECVD) dissociates silicon- and nitrogen-containing precursors in a glow discharge to build a cross-linked Si–N network within a bounded thermal budget; film density, hydrogen content, and intrinsic stress govern its erosion resistance during subsequent fluorocarbon etching.
- Process integration
- A continuous hard mask does not define contact positions by itself; it receives the lithography pattern via spin-on carbon (SOC) and anti-reflective stacks, preserving critical dimension (CD) stability after photoresist is consumed.
2 / 3
Etch the upper dielectric
After mask pattern transfer, SC Contact Trench Dielectric Etch anisotropically removes interlayer dielectric (SiO₂) to open a vertical contact trench. Further etching, cleaning and metallization complete the contact path.
- Mechanism
- High-C/F-ratio fluorocarbon plasma (C₄F₆/C₄F₈) uses lattice oxygen in SiO₂ to volatilize carbon as CO/CO₂ while fluorine radicals etch the oxide; on oxygen-free SiN gate caps/spacers and trench sidewalls, carbon-rich radicals polymerize into a protective CFₓ passivation film that delivers high SiO₂/SiN selectivity and vertical profiles.
- Process integration
- Self-aligned contacts (SAC) rely on encapsulation by the nitride gate cap and spacers: insufficient selectivity erodes the cap/spacer shoulder and causes gate-to-contact leakage, whereas excessive polymer deposition causes bowing or tapering that shrinks bottom contact area.
3 / 3
Polish after tungsten fill
Following bottom pre-clean, Ti silicide precursor, TiN barrier liner, and tungsten (W) overfill, CMP clears excess conductor from the dielectric surface and retains tungsten in the opening. Self-alignment also depends on insulating gate caps and spacers, and on etch selectivity.
- Mechanism
- Tungsten CMP uses slurry oxidizers to convert metallic W into a shear-softened surface oxide, leveraging pad contact-pressure differences to rapidly clear continuous field metal and stop selectively on the underlying dielectric to isolate adjacent plugs.
- Process integration
- CMP only eliminates field metal bridging and planarizes the top surface for downstream PMD recess and interconnect modules; self-aligned insulation depends on prior nitride cap/spacer encapsulation and etch selectivity, while low bottom contact resistance requires proper Ti silicide formation and void-free W fill.
Key ideas
With tight gate pitch in 14nm FinFETs, contact overlay margin is smaller than scanner alignment limits, so self-aligned contact (SAC) replaces pure lithographic alignment with material etch selectivity: step 165 PECVD SiN hardmask locks the top pattern, and step 173 carbon-rich fluorocarbon plasma (such as C₄F₆/C₄F₈) continuously etches SiO₂ while building a dense CₓFᵧ passivating polymer on SiN gate caps and spacer shoulders, guiding the opening along the insulating boundary without exposing the metal gate. After bottom breakthrough, interfacial silicidation, and CVD tungsten fill, step 194 CMP clears field metal and isolates individual plugs. Self-alignment is thus established by nitride boundaries and selective fluorocarbon chemistry, not by opening position or metal fill alone.
View the process comparison table
| Process dimension | Core mechanism and selectivity | Window mismatch risk and verification boundary |
|---|---|---|
| 165: PECVD SiN hardmask | Dense Si–N covalent network withstands prolonged ion bombardment, providing a rigid transfer mask from thin resist into thick ILD. | Thickness or stress mismatch amplifies trench line-edge roughness (LER) or sidewall taper drift; no contact opening is patterned yet. |
| 173: SAC selective dielectric etch | High-C/F plasma liberates oxygen from SiO₂ as volatile CO/CO₂ while building a protective CₓFᵧ polymer shield on oxygen-free SiN caps and spacers. | Excess polymer causes premature etch stop (open contact), whereas insufficient polymer facets the SiN shoulder and risks gate-to-contact bridging. |
| 194: tungsten fill and CMP | After CVD tungsten fills the contact trench, ferric-oxidizer alumina slurry clears field W and Ti/TiN barrier, stopping on dielectric to isolate plugs. | Slurry attack along a tungsten center seam opens keyhole voids; a filled cross-section does not prove low silicide contact resistance or low gate leakage. |
About this schematic
Omits multi-layer patterning after step 165, as well as bottom etch-stop breakthrough, wet polymer strip, raised source/drain silicidation, and Ti/TiN liner deposition after step 173; gate-cap and spacer shield details are not drawn to scale, and no measured contact resistance or TDDB data are shown.