40nm → 28nm · Architectural Node Evolution
40nm vs 28nm Semiconductor Process Comparison
From Planar Poly-Si Gate to High-k Metal Gate (HKMG) and Strain Engineering
40nm marks the physical scaling limit of conventional Poly/SiON planar technology. As one of the longest-lived nodes in industry history, 28nm introduced High-k Metal Gate (HKMG), Replacement Metal Gate (RMG) flows, and embedded SiGe channel strain engineering, slashing gate leakage by over 100x.
1. Key Physics Metrics & Device Parameters
The table below summarizes the key parametric shifts from 40nm to 28nm across gate stack, lithography pitch, electrostatics, and interconnect architecture:
| Metric | 40nm | 28nm | Physical Significance |
|---|---|---|---|
| Transistor Architecture | 2D Planar Bulk MOSFET | 2D Planar HKMG MOSFET | Maintains planar topology while overhauling gate materials |
| Gate Dielectric & EOT | SiO2 / SiON (~1.4nm physical) | ALD HfO2 (κ ≈ 22, EOT ~0.95nm) | 5x higher dielectric constant suppresses direct tunneling |
| Gate Electrode | Doped Poly-Silicon | Metal Gate Stack (TiN/TaN/TiAl) | Eliminates poly depletion, reducing Tinv by ~0.4nm |
| Contacted Poly Pitch (CPP) | ~140–160 nm | ~115–120 nm | Standard cell area shrinks by ~50% compared to 40nm |
| Core Operating Voltage (Vdd) | 1.1 V | 0.9 V | Quadratic dynamic power scaling delivers >30% energy efficiency |
| Channel Strain Mechanism | Standard thermal lattice | pMOS embedded SiGe uniaxial compressive | 30-50% hole mobility boost balances PMOS/NMOS drive ratio |
2. Gate Dielectric & Replacement Metal Gate (RMG)
40nm: Poly-Si + Thermal SiO2 → 28nm: ALD HfO2 + Gate-Last RMG Process
At 40nm, scaling SiO2 below 1.5nm led to exponential gate leakage. 28nm introduces ALD HfO2 high-k dielectric and gate-last RMG: dummy poly is wet-etched after high-temperature S/D activation anneals, followed by conformal work-function metal stacks and tungsten fill.
Physical Mechanism: EOT = t_phys × (3.9 / κ). ALD HfO2 leverages κ ≈ 22 to achieve sub-1nm electrical thickness from a 2nm physical film, suppressing direct quantum mechanical tunneling.
40nm Pre-CMP oxide covering wafer topology
28nm ALD HfO2 high-k film with sub-nanometer thickness precision
3. Isolation Engineering & STI Planarization
40nm: Conventional STI + Pixel Deep Trench → 28nm: High Aspect HARP CVD Oxide + High-Selectivity CMP
40nm CIS combines standard STI with multi-micron deep trench isolation (DTI) to eliminate pixel optical/electrical crosstalk. 28nm deploys HARP ozone-TEOS CVD to fill high-aspect active area gaps with zero voids, polished flat via high-selectivity slurry CMP.
Physical Mechanism: As active pitch scales, standard PECVD pinches off trench mouths before complete filling. HARP uses O3-TEOS surface-reaction kinetics to achieve seamless void-free filling.
40nm STI chemical mechanical planarization
28nm thermal pad oxidation relieving interface shear stress
4. Source/Drain Strain & Mobility Enhancement
40nm: Planar ion implantation + spike anneal → 28nm: Embedded SiGe (eSiGe) selective epitaxy
40nm formed junctions via tilted ion implantation and spike annealing. 28nm etches selective cavities in pMOS source/drain regions and epitaxially grows embedded SiGe with 25-35% Ge. The lattice mismatch imposes uniaxial compressive stress along the channel.
Physical Mechanism: Uniaxial compressive stress lifts valence band degeneracy between heavy and light holes, lowering effective hole mass and suppressing acoustic phonon scattering.