28nm → 14nm · Architectural Node Evolution
28nm vs 14nm Semiconductor Process Comparison
The Historic Leap from 2D Planar MOSFETs to 3D FinFET and Self-Aligned Double Patterning (SADP)
The 28nm-to-14nm transition represents the most profound transistor architecture revolution in 40 years: as 2D planar channels reached 20nm gate lengths, short-channel effects and DIBL caused catastrophic leakage. 14nm tri-gate FinFETs wrap the gate on three sides of a vertical silicon fin, restoring near-ideal electrostatics while introducing SADP pitch halving and Self-Aligned Contacts (SAC).
1. Key Physics Metrics & Device Parameters
The table below summarizes the key parametric shifts from 28nm to 14nm across gate stack, lithography pitch, electrostatics, and interconnect architecture:
| Metric | 28nm | 14nm | Physical Significance |
|---|---|---|---|
| Transistor Configuration | 2D Planar Bulk | 3D Tri-Gate FinFET | 3D electrostatic control eliminates punch-through leakage |
| Patterning Methodology | ArFi Single Exposure (Pitch ~80nm) | SADP Pitch Halving (Fin Pitch ~48nm) | Pitch halving bypasses immersion optical diffraction limits |
| Contacted Poly Pitch (CPP) | ~115–120 nm | ~78 nm | >32% tighter gate pitch slashes overall chip area by ~50% |
| Subthreshold Swing (SS) | ~85–95 mV/dec | ~65–70 mV/dec (near theoretical 60) | Sharper turn-off characteristics reduce OFF-state leakage >10x |
| Core Operating Voltage (Vdd) | 0.9 V | 0.70–0.75 V | Voltage reduction cuts dynamic switching energy by >50% |
| Contact Alignment Margin | Photolithographic overlay constrained | Self-Aligned Contact (SAC) cap protection | Allows contact overlap without risk of catastrophic gate shorts |
2. 3D Fin Architecture & Tri-Gate Electrostatics
28nm: Planar gate control (top only) → 14nm: Tri-gate vertical silicon fin wrap
28nm planar devices rely on bulk depletion to suppress leakage. When gate length shrinks, drain field punches through. 14nm FinFET etches vertical fins (~8nm wide, ~40nm tall) wrapped on three sides by the gate, eliminating ungateable bulk regions and delivering steep subthreshold turn-off.
Physical Mechanism: Short channel natural length λ = sqrt((ε_ch / 2ε_ox) × t_fin × t_ox). The narrow fin width t_fin dramatically shrinks λ, ensuring gate electrostatic dominance.
28nm pad nitride deposition as planar active mask
14nm FCVD oxide filling dense sub-48nm fin trenches void-free
3. Self-Aligned Double Patterning (SADP)
28nm: Single 193nm ArFi Litho & Etch → 14nm: Sacrificial Mandrel + Spacer Deposition & Pull
Fin pitch of ~48nm exceeds the optical Rayleigh limit (~80nm) of 193nm immersion lithography. SADP patterns relaxed mandrels, deposits ultra-conformal spacers along sidewalls, anisotropically etches horizontal spacer layers, and selectively etches the core mandrel. One lithographic feature splits into two self-aligned lines with half pitch.
Physical Mechanism: Spacer thickness is governed strictly by CVD/ALD deposition time, achieving sub-nanometer CD control (3σ < 0.5nm) independent of lens aberrations.
28nm pad oxidation
14nm STI conformal liner oxide repairing fin sidewall etch damage
4. Self-Aligned Contact (SAC) & Gate Cap
28nm: Masked contact hole photolithography → 14nm: Self-Aligned Contact (SAC) with SiN gate cap
At sub-80nm CPP, overlay misalignment during contact lithography would breach the gate metal, causing catastrophic shorts. 14nm recesses the metal gate and deposits a dense SiN cap. Selective dielectric chemistry stops abruptly on the SiN cap, allowing self-aligned contact trench etching with zero shorting risk.
Physical Mechanism: Selective fluorocarbon plasma generates protective fluoropolymer films on SiN while rapidly volatilizing SiO2, achieving >15:1 selectivity.
14nm SAC Hardmask: Acts as etch stop for self-aligned contact openings