How are isolation trenches formed in silicon?
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Open the mask
Purple marks the patterned mask layer; gray is the single-crystal silicon substrate. Start by locating the lateral isolation boundary defined by the mask opening before tracking silicon etching, interface oxidation, and bulk dielectric fill.
Shallow trench isolation (STI) establishes electrical and mechanical boundaries between neighboring active regions. Starting from a multilayer hard-mask opening, follow anisotropic silicon trench etching, dry stripping and surface conditioning, thermal liner oxidation, and high-aspect-ratio process (HARP) oxide overfill.
In-situ multilayer hard-mask transfer opens the isolation window above the silicon substrate, exposing the target silicon surface while shielding the flanking active areas (AA). The lateral critical dimension (CD) is now locked by the mask opening, while bulk silicon remains unetched.
- Mechanism
- Upper transfer layers, organic hard masks, silicon nitride (SiN), and pad oxide differ in bond energy and byproduct volatility. Stepwise plasma etch selectivity transfers the pattern downward without exhausting thin photoresist during subsequent deep silicon etching.
- Process integration
- Mask sidewall verticality and remaining thickness margin directly govern aperture fidelity during subsequent silicon trench etching; mask edge erosion translates directly into active-area (AA) width variation.
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Etch the silicon trench
Anisotropic plasma etching advances downward through the mask opening into single-crystal silicon, forming an isolation trench with controlled depth and sidewall taper. Compared with the previous state, the mask constrains lateral position while vertical geometry is established in silicon.
- Mechanism
- Plasma silicon etching combines reactive radical chemistry, directional ion-assisted surface activation, and volatile byproduct desorption; ion directionality balanced against sidewall passivation controls trench taper and suppresses lateral undercut.
- Process integration
- This step outputs the silicon trench geometry alongside residual organic mask and plasma-damaged surfaces. Subsequent dry stripping ashes the carbon backbone and wet cleaning exposes clean silicon walls; any silicon geometry lost during etching cannot be recovered by cleaning.
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Form the liner oxide
On the clean silicon trench walls and floor exposed after stripping and wet cleaning, controlled thermal oxidation grows a thin, continuous liner oxide. It follows the trench contour by consuming surface silicon without filling the bulk trench volume.
- Mechanism
- Thermal oxidation drives oxygen species to react with surface silicon, consuming plasma-induced subsurface lattice damage, reducing interface dangling-bond states, and rounding sharp top and bottom trench corners to increase curvature radius and suppress local electric-field crowding.
- Process integration
- Establishing a chemically and structurally stable Si/SiO₂ interface before bulk dielectric fill suppresses parasitic corner inversion in planar MOSFETs (double-hump Id–Vg subthreshold leakage), though excessive oxidation-induced volume expansion must be bounded to avoid slip dislocations.
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Fill with isolation oxide
Over the rounded and passivated liner surface, high-aspect-ratio process (HARP) oxide deposition intentionally overfills the trench and covers the field surface, converting the open cavity into a continuous solid isolation dielectric.
- Mechanism
- Ozone-assisted TEOS sub-atmospheric thermal CVD (SACVD) operates in a surface-reaction-controlled regime for highly conformal growth; however, overly vertical or re-entrant walls accelerate top closure (pinch-off) before opposing fronts merge, trapping a low-density central seam or void.
- Process integration
- Intentional overfill provides margin for subsequent high-temperature densification annealing (healing central seams and stabilizing stress coupled into the channel) and SiN-stop CMP planarization; the fill cross-section alone cannot replace post-anneal density and isolation leakage verification.
Key ideas
Front-end STI integration is a coordinated stress- and interface-engineering sequence rather than simple trench cutting and filling: the SiN hardmask serves as an etch mask during AA Etch, survives step 9 stripping, and later acts as the oxide CMP stop layer; thermal liner oxidation at step 15 consumes plasma-damaged surface silicon to heal lattice defects, passivate dangling bonds, and round trench corners against corner field crowding; HARP (O₃/TEOS) oxide at step 18 then achieves bottom-up void-free gap fill over the liner via radical-assisted surface migration. Cross-section reading must separate the mid-step mask-open intermediate from the etched trench final state, while recognizing that geometry alone does not verify interface-state density or leakage.
View the process comparison table
| Process dimension | Core mechanism and selectivity | Window mismatch risk and verification boundary |
|---|---|---|
| Mask opening (step 8 intermediate) | Fluorocarbon plasma anisotropically opens SiN and pad oxide, locking the active layout into the inorganic hardmask and exposing silicon. | Opening taper or CD error transfers directly into silicon trench CD drift; schematics cannot replace inline CD metrology. |
| Silicon trench etching (step 8 final) | Directional ion bombardment and sidewall passivation synergistically etch single-crystal silicon with controlled sidewall taper and bottom rounding. | Overly vertical sidewalls induce HARP pinch-off voids, while shallow taper consumes active width; subsurface lattice damage requires thermal liner healing. |
| Dry resist stripping (step 9) | Oxidizing plasma converts residual resist and carbon polymers into volatile CO, CO₂, and H₂O with high selectivity to silicon and SiN. | Incomplete ashing carbonizes polymers in high-temperature oxidation furnaces and pins defects; excessive bombardment roughens exposed silicon. |
| Liner oxidation (step 15) | High-temperature thermal oxidation consumes damaged surface silicon to grow a dense Si–O–Si network, saturating dangling bonds and rounding corners. | An overly thin liner fails to suppress corner subthreshold hump leakage and fill tensile stress; interface-state density requires electrical testing. |
| HARP oxide fill (step 18) | Sub-atmospheric O₃/TEOS reaction generates mobile surface precursors for bottom-up seamless trench fill and field overburden. | Insufficient precursor mobility leaves center seams that open into divots during HF cleans; geometric fill does not prove post-anneal densification. |
About this schematic
The four cross-sections represent selected milestones rather than consecutive steps: wet cleans and corner conditioning at steps 10–14, post-liner steps 16–17, and post-fill HARP densification anneal and STI oxide CMP are omitted. The schematics align morphological progression and do not depict true film scale, subsurface lattice damage, or interface-trap distributions.