Where is the first pattern during the second exposure?
1 / 3
Define the first pattern
E1 and E2 denote the two interleaved contact pattern subsets. Purple marks the active photoresist of the current pass; blue marks the underlying hard-mask memorization layer carrying transferred patterns. Dashed outlines mark positions only.
When neighboring gate contact pitch shrinks below the single-exposure immersion Rayleigh resolution limit, optical diffraction merges adjacent features. Follow LELE (Litho-Etch-Litho-Etch) double patterning through E1 exposure and hard-mask memorization, interleaved E2 exposure, and integrated dielectric/gate-cap etching.
Gate Contact_E1 Lithography defines the first sparse subset of positions (E1) in photoresist. Subsequent SiON and memorization-layer etching transfers it into underlying inorganic material, preserving the first set of positions after resist strip.
- Mechanism
- Pitch splitting enlarges the feature spacing on each mask so spatial frequencies remain within the optical imaging resolution window; photoacid-catalyzed deprotection and development form the resist opening, which anisotropic etching locks into a solvent-resistant inorganic hard mask.
- Process integration
- Without transferring E1 into the underlying hard mask first, solvents and baking during the second spin-coat pass would dissolve or deform the first photoresist pattern; hard-mask memorization is the physical prerequisite for pass two.
2 / 3
Form the second pattern
After stripping the first resist and recoating the transfer stack, the E2 resist pattern is formed while E1 is already retained in the underlying memorization material. Different layers now carry the two pattern sets into subsequent integrated etching.
- Mechanism
- The second optical exposure likewise operates at the relaxed subset pitch to avoid diffraction bridging; subsequent SiON etching writes E2 into the shared memorization layer, merging two sub-resolution subsets onto a single hard-mask plane.
- Process integration
- E2 placement accuracy relies on optical overlay alignment to underlying marks. Because E1 and E2 originate from two separate exposures, any E1-to-E2 overlay shift directly converts into asymmetric contact-to-contact spacing variation.
3 / 3
Transfer both sets into openings
Gate Contact Integrated Etch transfers both retained sets of positions downward into dielectric openings and opens the silicon nitride gate cap. Overlay error can remain between the two passes: retaining both patterns does not ensure exact alignment.
- Mechanism
- Integrated etching stages plasma selectivity: it first etches interlayer dielectric toward the protective silicon nitride gate cap (an insulating dielectric cap rather than a metal cap) and then intentionally opens the SiN cap to expose the underlying metal gate while passivating sidewalls.
- Process integration
- Although both subsets are etched downward simultaneously during integrated etching, prior E1-to-E2 overlay errors and sub-10nm stochastic CD variations are already locked into the memorization mask and cannot self-correct; excessive shift encroaching on protected regions still risks gate-to-contact shorts.
Key ideas
When 7nm gate-contact (CB) pitch drops below the Rayleigh diffraction limit of single-exposure 193nm immersion lithography, LELE (Litho-Etch-Litho-Etch) splits the layout into relaxed-pitch sub-masks to avoid optical proximity crosstalk: step 305 exposes the E1 sub-mask, which is then etched into an underlying inorganic hardmask (pattern-memory layer) before resist strip; step 314 coats a fresh organic planarizing stack (OPL/SOC) over the E1 topography and patterns the E2 sub-mask above it, placing E1 and E2 in distinct physical carrier layers; step 319 integrated etching then merges both coordinate sets into dense target openings. Separating carriers overcomes the optical limit but converts E1-to-E2 scanner overlay error directly into pitch asymmetry between adjacent openings.
View the process comparison table
| Process dimension | Core mechanism and selectivity | Window mismatch risk and verification boundary |
|---|---|---|
| 305: E1 first lithography and transfer | Layout splitting halves spatial frequency to boost NILS optical contrast, then etches and locks E1 coordinates into the underlying inorganic memory hardmask. | E1 dose or focus drift alters the first-set CD baseline, causing systematic odd/even contact diameter mismatch. |
| 314: E2 second lithography and dual carriers | Spin-on planarization levels E1 relief and suppresses reflection so E2 resist coexists in a separate physical layer above the retained E1 hardmask. | Reworking E2 resist preserves underlying E1, but E2-to-E1 overlay error directly compresses dielectric spacing between adjacent contacts. |
| 319: integrated opening etch | Multi-stage plasma switching transfers E2 and then uses the composite hardmask to etch both E1 and E2 locations simultaneously into the target dielectric. | Loading differences between twice-exposed and once-exposed paths can skew E1/E2 depth or taper; opening formation does not imply completed cleaning or metal fill. |
About this schematic
Uses two lateral groups to illustrate the dual-carrier memory mechanism; dashed outlines mark spatial coordinates rather than added material. Steps 306–313 E1 hardmask etch, strip, shrink, and second-pass tri-layer coating, steps 315–318 intermediate transfer, and post-319 metallization are omitted; resist tone and true film scale are unspecified.