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Explore BEOL interconnect physics — copper dual-damascene, barrier/seed layers, electromigration, and RC delay scaling. Learn how metallization schemes evolve from 28nm through 7nm and beyond.

67 articles
self-aligned contact oxidecopper dishing erosionpre-metal dielectricself-aligned contacttungstenvertical interconnect access

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Technical Blog

Deep dive into the physics and integration logic of semiconductor manufacturing

InterconnectMay 31, 20266 min read

Principles of Self-Aligned Contact Oxide: Physics, Process Integration, and Advanced Node Scaling

In early planar complementary metal-oxide-semiconductor (CMOS) technology, contact placement was governed primarily by lithographic registration tolerances, where overlay errors…

InterconnectMay 30, 20265 min read

Controlling Surface Topography in Advanced BEOL: The Physics and Process Principles of Copper Dishing and Erosion

In modern integrated circuit manufacturing, back-end-of-line (BEOL) metallization is responsible for routing electrical signals across billions of transistors.

InterconnectMay 28, 20266 min read

Demystifying the Pre-Metal Dielectric: Physics, Process Integration, and Advanced Node Evolution

In the fabrication of modern integrated circuits, the boundary between active semiconductor devices and the complex network of metal interconnects represents a critical interface…

InterconnectMay 28, 202612 min read

Self-Aligned Contacts: Selective Etching, Protective Boundaries and Integration

A self-aligned contact (SAC) uses retained dielectric protection and selective etching to open a source/drain connection while protecting the neighboring gate. Lithography still places the opening. Self-alignment provides tolerance to some pattern overlap; it does not eliminate overlay error or permit unlimited loss of the protective dielectric.

InterconnectMay 25, 20265 min read

Tungsten in Semiconductor Contacts

Why is tungsten used in semiconductor contacts? Follow the interface, fill and planarization that form an isolated conductive plug.

InterconnectMay 25, 20265 min read

Vertical Interconnect Access (Via): Physical Principles, Integration Logic, and Advanced Node Evolution

A via connects two wiring levels. Follow the actual Via 1 photo and dielectric etch steps, then compare the earlier contact examples without confusing the two.

InterconnectMar 15, 20269 min read

Copper Dual Damascene: From Trenches and Vias to Fill and CMP

Copper dual damascene forms a horizontal trench and a connecting via in dielectric, then includes both in one metallization and CMP cycle. “Dual” describes the organization of a line and a via. It does not mean simply etching twice or growing two metal levels at once.

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SemiFlows

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© 2026 SemiFlows. All rights reserved.

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