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SemiFlows
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Explore the physics of energetic ion bombardment for dopant introduction. Covers range/straggle theory, channeling effects, amorphization, and damage annealing mechanisms in advanced transistor fabrication.

26 articles
implant dose vs active dopingLDD vs halo implantselective eSi source-drain integration at 7nmselective Si and SiGe epitaxy integration at 14nmselective SiGe epitaxy in 28nm source-drain14nm FinFET well and channel implant integration process flow

Related Process Flows

7nm FinFET7nm714 steps14nm FinFET14nm362 steps28nm Planar Flow28nm266 steps

Technical Blog

Deep dive into the physics and integration logic of semiconductor manufacturing

Ion ImplantationSep 11, 20265 min read

Implant Dose vs Active Dopants: Count the Right Thing

Understand why delivered implant dose, chemical concentration, active dopants and mobile carriers are different quantities.

Ion ImplantationSep 11, 20265 min read

LDD vs Halo Implants: Two Different Electrostatic Jobs

Compare LDD and halo doping through their locations, polarities, electrostatic roles and resistance tradeoffs.

Ion ImplantationSep 3, 20266 min read

Selective eSi Source-Drain Integration at 7nm: Physics, Chemistry, and Module Integration

Function in the Complete Flow In sub-10nm logic manufacturing, the integration of selective epitaxial silicon (eSi) in the source and drain regions of n-channel Field-Effect…

Ion ImplantationSep 3, 20266 min read

Selective Si and SiGe Epitaxy Integration at 14nm: Principles, Strain Kinetics, and Integration Logic

Function in the Complete Flow In modern 14nm FinFET logic fabrication, raised source/drain epitaxy plays a foundational role by simultaneously managing parasitic series…

Ion ImplantationSep 3, 20266 min read

Principles of Selective SiGe Epitaxy in 28nm Source-Drain Integration

<article Function in the Complete Flow In advanced p-type metal-oxide-semiconductor (pMOS) field-effect transistors within the 28nm Planar Flow, enhancing carrier transport…

Ion ImplantationAug 11, 20265 min read

14nm FinFET Well and Channel Implant Integration Process Flow: Principles, Mechanisms, and Module Dependencies

Role in the Complete Flow The well and channel implant integration module sits at a critical juncture in the 14nm FinFET process flow, bridging the gap between fin…

Ion ImplantationAug 11, 20266 min read

14nm FinFET Epitaxial Silicon Source-Drain Integration Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow The 14nm FinFET epitaxial silicon source-drain (SD_ESI) module occupies a pivotal position in the front-end-of-line (FEOL) process sequence, sitting…

Ion ImplantationAug 11, 20266 min read

14nm FinFET Embedded Silicon Germanium Source-Drain Integration: Process Flow Principles and Strain Engineering Mechanisms

Role in the Complete Flow In the 14nm FinFET technology node, the embedded silicon germanium (eSiGe) source-drain module serves as one of the most performance-critical…

Ion ImplantationAug 11, 20266 min read

28nm Planar Well and Channel Implant Integration Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow The 28nm Planar well and channel implant integration represents a critical inflection point in the front-end-of-line (FEOL) process sequence.

Ion ImplantationAug 11, 20265 min read

28nm Planar Source-Drain Integration Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow The source-drain (SD) module in the 28nm planar logic flow sits at a pivotal position within the front-end-of-line (FEOL) sequence.

Ion ImplantationAug 11, 20266 min read

28nm Planar Well Formation Process Flow: Integration Logic, Device Physics, and Module Dependencies

Role in the Complete Flow The well formation module in the 28nm planar process flow serves as the foundational doping architecture upon which all subsequent transistor…

Ion ImplantationAug 11, 20266 min read

40nm BSI CMOS Image Sensor N FD IIP Photolithography Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow In a 40nm backside-illuminated (BSI) CMOS image sensor (CIS), the N-type floating-diffusion ion implantation photolithography (N FD IIP - Photo) step…

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SemiFlows

Semiconductor process knowledge — flow visualization + Flow-aware, evidence-linked Q&A

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