Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
Barrier vs Liner: Different Jobs at a Metal Interface
Compare diffusion barriers, liners and seed roles without treating interface functions as interchangeable material names.
Contact vs Interconnect Resistance: Follow the Current
Separate contact interfaces, access regions and metal lines to understand the resistance of a complete current path.
Single vs Dual Damascene: Follow the Fill Sequence
Compare single and dual damascene by tracking when vias and lines are filled, planarized and connected.
Via-First vs Trench-First: Track the Exposed Surfaces
Follow exposed surfaces and temporary materials to understand via-first and trench-first dual damascene.
14nm M2 Copper CMP Mechanism: Physics, Chemistry, and Integration Logic
Function in the Complete Flow In advanced multi-level interconnect architectures, back-end-of-line (BEOL) structures rely on copper metal lines to route power and high-speed…
Gate-Contact Tungsten Fill and CMP Integration Principles in 14nm FinFET Technology
Function in the Complete Flow In advanced middle-of-the-line (MOL) processing for 14nm FinFET architectures, gate contact metallization serves as the critical conductive bridge…
Contact Barrier (CB) Dielectric Etch in 28nm: Physics, Integration Mechanisms, and Device Reliability
Function in the Complete Flow In a 28nm Planar process flow, the contact barrier (CB) dielectric etch is the pivotal pattern-transfer step that opens vertical access vias through…
Thermocompression Bonding Mechanism for Stacked CIS: Physical Principles and Integration Dynamics in 40nm BSI Sensors
Function in the Complete Flow In modern imaging architectures, the back-side illuminated (BSI) CMOS image sensor (CIS) relies on heterogeneous vertical integration to separate…
Top Passivation Oxide-Nitride Stack Integration in 7nm FinFET Technology: Physics, Mechanisms, and BEOL Protection
Function in the Complete Flow In advanced 7nm technology platforms, the back-end-of-line (BEOL) interconnect hierarchy terminates at the uppermost metallization level, designated…
Tungsten Contact Fill and Chemical Mechanical Planarization in 28nm Planar Process Architecture
Function in the Complete Flow In 28nm planar CMOS architectures, tungsten contact plug formation and subsequent contact chemical mechanical planarization (CMP) form the critical…
Via-Contact Metal Fill and CMP in 7nm FinFET Integration: Mechanics, Planarization, and Module Interactions
Function in the Complete Flow In advanced logic manufacturing, the Middle-of-Line (MOL) module acts as the critical electrical and physical bridge connecting sub-surface…
14nm FinFET Gate Contact Integration: Process Flow, Physics, and Module Dependencies Explained
Role in the Complete Flow In the 14nm FinFET process flow, the gate contact (CONTACT_CG) module serves as the primary vertical electrical connection between the buried…