What “dual” describes
Copper dual damascene forms a horizontal line trench and its connecting via in dielectric, then includes both in one metallization and planarization cycle. The line carries a connection along a level; the via connects it to another level. “Dual” does not simply mean etching twice or completing two independent metal levels at once.
In the illustrated 28nm V1/M2 example, locate existing M1 first. Then trace the future M2 trench and the downward V1 connection. These cavities describe where metal will go; dielectric patterning has not yet created the final copper conductor.
Process checkpoint
Understand V1M2 Etch in context
Trace V1 from the M2 trench to M1, then compare the copper-filled and post-CMP structures.
Process context for “Copper Dual Damascene: From Trenches and Vias to Fill and CMP”: 28nm Planar Flow · M2 · Step 218
Dual damascene: define cavities, then form interconnectWhy the incoming cavity and interface matter
The patterned dielectric provides geometry and electrical separation. A barrier controls unwanted copper transport into surrounding material, while a conductive seed supports subsequent electroplating. Coverage and continuity must be considered throughout the feature, including its corners and lower regions. The general interconnect stack therefore has several jobs that a single “metal fill” label can hide.
During plating, copper is deposited on the conductive surface. Filling requires growth inside the feature to keep pace with growth near its opening. The plating literature describes how suppressing and accelerating influences shape this distribution, and why incoming seed condition, wetting, feature geometry and deposition behavior must be considered together. A uniform top surface does not prove that the interior is free of voids.
Overburden connects filling to polishing
After filling, copper also remains above the dielectric as overburden. Its distribution sets the starting condition for CMP. The plating process must leave enough material for the intended structures, while the following removal must clear the unwanted connection across the upper surface. Pattern-dependent plating topography can therefore become a polishing problem.
CMP combines chemical surface reactions with mechanical removal. Dishing describes a recessed metal surface relative to its surroundings; erosion describes broader material loss in a patterned region. Both can change the resulting conductor geometry. Increasing polishing alone is not a universal correction: clearing residual overburden and preserving the intended conductor are competing requirements.
Follow the actual V1/M2 handoff
At Step 218, identify the etched M2 trench and the via toward M1. Step 222 fills the cavity with copper, and the later image at Step 224 shows the result after CMP. Intervening interface preparation, barrier and seed work remain part of the sequence. Compare the same locations across the views instead of treating the drawings as interchangeable pictures of a finished wire.
Before filling, ask whether the intended connection and isolating dielectric remain correctly defined. After filling, ask whether the connected volume has been occupied. After CMP, ask whether unwanted upper metal has been removed while the line and via remain continuous. The drawings locate these questions; electrical and materials evidence is needed to answer them fully.
Keep failure mechanisms distinct
An unfilled region or damaged interface can restrict the intended current path. Remaining upper metal can connect structures that should be separate. Barrier damage can create a transport path into the surrounding material, while excessive removal can reduce conductor dimensions. These failures require different evidence and different corrections.
The node label alone cannot specify a universal barrier, conductor, plating sequence or reliability limit. The transferable lesson is the dependency: dielectric geometry and interface preparation constrain filling, and the filled topography constrains conductor separation during CMP.
Follow the actual structures
The M2 trench and downward via form cavities above existing M1. This step removes dielectric, not the final copper wire.
CMP clears upper excess copper while retaining dielectric-bounded interconnect, including its lateral and downward portions.
Sources for these cross-sections
References
Review—Management of Copper Damascene Plating
R. Carpio, A. Jaworski · Journal of the Electrochemical Society
Silicon VLSI Technology - Full
James D. Plummer, Michael D. Deal, Peter B. Griffin
Silicon VLSI Technology · ISBN 978-0130850379