Dry Etching: Principles, Physics, and Role in Advanced Semiconductor Manufacturing

Introduction

Dry etching is one of the most critical pattern-transfer techniques in modern semiconductor manufacturing. Unlike wet etching, which relies on liquid chemical solutions to dissolve material, dry etching uses gas-phase species—most commonly in the form of a plasma—to remove material from a substrate surface. The term "dry" reflects the absence of liquid etchants, and because a plasma is almost always involved, the process is frequently called plasma etching or reactive ion etching (RIE).

The importance of dry etching in integrated circuit fabrication cannot be overstated. When feature sizes entered the sub-micron regime, wet etching became fundamentally incompatible with the required dimensional control. Directional etching is needed to minimize underetching and etch bias, which then allows smaller and more tightly packed structures [T1]. Plasma-based dry etching overcomes the limitations of wet etching by enabling anisotropic material removal, where etching proceeds predominantly in the vertical direction while the sidewalls remain protected by passivating films.

Beyond anisotropy, dry etching offers superior uniformity, repeatability, and throughput compared to wet processes. It avoids the handling of large volumes of liquid chemical waste and integrates well with automated single-wafer manufacturing systems. From gate stack definition and shallow trench isolation to contact formation and back-end-of-line (BEOL) interconnect patterning, virtually every critical feature transfer step relies on dry etching.

Physics & Mechanism

The Nature of Plasma

At the heart of dry etching lies plasma, often described as the fourth state of matter. When an etch gas is introduced into a low-pressure vacuum chamber and subjected to a radio-frequency (RF) electric field, free electrons gain kinetic energy and collide with neutral gas molecules, leading to ionization, excitation, and dissociation.

The resulting plasma is a quasi-neutral mixture composed of positive ions, electrons, radicals, and neutral molecules. Electrons, due to their low mass, respond rapidly to the alternating electric field, while heavier ions experience an time-averaged electric potential. Chemically reactive neutral species (radicals) provide chemical reactivity, whereas accelerated ions provide directional physical kinetic energy.

Ion Bombardment and Chemical Reaction

Material removal in dry etching proceeds through three primary mechanisms: purely physical sputtering, purely chemical etching by radicals, and ion-assisted energetic etching.

In purely physical sputtering, energetic positive ions accelerated across the plasma sheath strike the wafer surface, knocking substrate atoms loose through direct momentum transfer. Sputtering is directional but suffers from low etch selectivity and potential lattice damage. Purely chemical etching occurs when uncharged radicals diffuse to the wafer surface and react with target atoms to form volatile products. Chemical etching provides high material selectivity but operates isotropically, undercutting mask edges.

Reactive ion etching achieves anisotropy and reasonable rate through a synergistic mechanism. This energetic ion bombardment causes a disruption of a halogenated chemisorbed layer and induces chemical reactions that lead to the formation of volatile products [P1]. Direct vertical ion impact continuously removes passivating surface layers at the bottom of a feature, allowing chemical radicals to react rapidly with the exposed substrate, while un-bombarded sidewalls remain protected by passivation.

The Role of the Plasma Sheath

Because electrons are vastly more mobile than positive ions, they rapidly escape to the chamber walls upon plasma ignition. This creates a net positive potential within the bulk plasma relative to surrounding surfaces, establishing a narrow boundary region known as the plasma sheath.

An electric field forms across the sheath, directed perpendicular to the wafer surface. Positive ions entering the sheath are accelerated across this potential drop, arriving at the substrate with near-normal incidence. The magnitude of this sheath potential drop—referred to as the DC self-bias—determines the kinetic energy of striking ions, governing the balance between physical sputtering and chemical reaction enhancement.

Inductively Coupled Plasma and Decoupled Control

In conventional capacitively coupled plasma (CCP) systems, a single RF power source drives both plasma generation and sheath potential. Consequently, increasing plasma density automatically increases ion kinetic energy, making it difficult to achieve high etch rates without increasing surface damage.

Inductively coupled plasma (ICP) configurations overcome this limitation by utilizing separate power sources. An inductive coil source generates high-density plasma to control radical and ion flux, while an independent capacitive RF bias applied to the electrostatic chuck controls ion energy. Decoupling plasma density from ion energy enables process engineers to optimize directional vertical etching while minimizing lattice degradation.

Process Principles

Gas Chemistry and Selectivity

Gas chemistry selection determines the material selectivity—the ratio of the target layer etch rate to the etch rate of the underlying substrate or masking layer. Etch chemistries are tailored based on the volatility of resulting chemical by-products:

• Silicon and Silicon Dioxide: Fluorine-based gases (such as CF4, SF6, or CHF3) yield volatile SiF4 compounds.
• Polysilicon Gates: Chlorine and hydrogen bromide (HBr) chemistries provide anisotropic profiles and high selectivity over thin underlying gate oxides.
• Metals (e.g., Aluminum): Chlorine-based chemistries form volatile AlCl3 species.
• Organic Polymers: Oxygen-based plasmas react with polymeric materials to form CO, CO2, and H2O vapors.

Adding passivation-promoting species (such as fluorocarbon precursors) or oxidizers alters the balance between material removal and sidewall film deposition, enabling precise control over feature profile angles.

Pressure and Mean Free Path

Chamber pressure directly dictates the mean free path of gas-phase particles. At lower chamber pressures, the mean free path increases, minimizing collisions within the plasma sheath. This preserves the vertical alignment of energetic ions, promoting highly anisotropic profiles.

Conversely, higher chamber pressures decrease the mean free path, increasing ion scattering and neutral radical density. This shifts the process toward isotropic chemical etching, increasing total etch rate and selectivity at the expense of profile directionality.

Ion Energy, Flux, and Damage Trade-offs

Increasing substrate bias power raises ion kinetic energy, improving sidewall verticality and enhancing the removal of non-volatile surface residue. However, higher ion energy increases sputtering of mask edges (faceting) and drives defects into underlying crystal lattices.

Conversely, increasing ion flux while maintaining low ion energy maintains high material removal rates without causing structural breakdown in fragile substrate interfaces. Managing this tradeoff is essential when patterning delicate device features.

Proximity and Loading Effects

Etch outcomes depend heavily on local feature density and geometry:

• Micro-loading: Highly dense feature arrays consume reactive radicals faster than open regions, leading to local radical depletion and reduced etch rates compared to isolated features.
• Aspect-Ratio Dependent Etching (ARDE): As narrow trenches etch deeper, high aspect ratios restrict the transport of neutral etchant radicals to the bottom and impede the escape of volatile by-products, causing deeper or narrower features to etch more slowly.
• Etch Proximity Correction (EPC): To offset these variations, layout design rules incorporate model-based corrections, adjusting drawn mask dimensions to ensure uniform critical dimensions (CD) across dense and isolated circuit structures.

Challenges & Failure Modes

Etch Bias and CD Control

Etch bias represents the difference between the resist mask dimension and the final etched feature size. Sub-nanometer variations in bias disrupt transistor drive currents and interconnect resistance. Managing etch bias requires tight control over mask erosion, sidewall passivation thickness, and ion scattering angles.

Micro-trenching

Micro-trenching occurs when energetic ions strike sloped feature sidewalls at glancing angles and reflect toward the outer edges of the feature floor. This localized concentration of ion flux increases the physical etch rate at the trench corners, forming sharp grooves that can disrupt underlying oxide integrity or cause void formation during subsequent film deposition.

Plasma-Induced Damage and the Antenna Effect

PID is well known to degrade both gate dielectric and metal-oxide-semiconductor field-effect transistors (MOSFETs) reliability . During plasma processing, conductive interconnect lines act as charge-collecting antennas. When exposed to spatial variations in plasma potential, these conductors collect non-uniform charge fluxes, driving current through thin gate dielectrics and causing premature breakdown or threshold voltage shifts.

Etch Stop Failures and Selectivity Loss

When sidewall passivation chemistry becomes overly dominant relative to ion redirection, protective polymer layers accumulate across feature floors faster than ions can clear them. This results in an unwanted etch stop, halting vertical progression before reaching the desired depth. Conversely, insufficient selectivity against underlying stop layers leads to substrate punch-through.

Surface Roughness and Subsurface Damage

Physical bombardment by energetic ions can disrupt the surface morphology of single-crystal substrates, creating lattice dislocations, amorphization, and atomic mixing. In wide-bandgap and compound semiconductors, ion impact creates surface states that trap charge carriers, requiring specialized post-etch surface recovery treatments.

Technology Node Evolution

28nm: Establishing Anisotropic Etching Baselines

At the 28nm planar process node, dry etching established stringent requirements for gate profile symmetry and critical dimension control. Chlorine and HBr plasma chemistries replaced wet processes for etching polysilicon gate stacks, relying on halogen passivation layers to maintain vertical profile sidewalls while stopping selectively on thin gate dielectrics.

14nm: FinFET Three-Dimensional Profile Engineering

The adoption of the 14nm FinFET architecture shifted dry etching from planar pattern transfer to three-dimensional profile shaping. Etching tall, narrow silicon fins for fin field effect transistors required extreme verticality, low sidewall roughness, and highly uniform fin height across the wafer. ICP systems equipped with hard mask schemes replaced resist-only masks to maintain structural integrity during extended plasma exposure.

7nm and Beyond: Multiple Patterning and Atomic-Scale Control

As feature pitches scaled past single-exposure optical limits, self-aligned multiple patterning strategies—such as self-aligned double patterning (SADP) and quadruple patterning (SAQP)—became mandatory before full implementation of extreme ultraviolet lithography. In these schemes, spacer etch processes must selectively remove horizontal dielectric films while leaving vertical sidewall spacers perfectly intact.

At the 7nm node and beyond, atomic layer etching (ALE) emerged as a complement to traditional continuous RIE. ALE utilizes cyclic, self-limiting reactions—alternating surface adsorption and low-energy ion removal steps—to achieve monolayer-level depth precision with minimal physical damage. This atomic-scale precision is vital when etching work-function metal stacks in high-k metal gate architectures and patterning delicate low-k dielectric materials in modern BEOL interconnects.

Related Processes

Dry etching operates within an integrated manufacturing flow, closely tied to complementary processing steps:

• Lithography: Defines the photolithographic mask patterns that dry etching transfers into underlying substrates. Line-edge roughness in photoresist directly propagates into etched trench profiles.
• Planarization: Following pattern transfer and dielectric deposition, chemical mechanical planarization removes topography, establishing flat surfaces for subsequent photolithography levels.
• BEOL Metallization: In copper dual damascene flows, dielectric trench and via etching determines structural profiles; smooth, slightly tapered trench sidewalls prevent void formation during barrier deposition and electroplating.
• Doping and Thermal Steps: Dry etching defines hard mask and gate dimensions prior to ion implantation. Subsequent thermal treatments, such as rapid thermal annealing, active dopants and repair physical lattice defects caused by ion bombardment.

Future Outlook

As device topologies transition toward gate-all-around (GAA) nanosheets and 3D integrated structures, dry etching face stringent requirements for lateral material selectivity and isotropic precision. Nanosheet release steps demand isotropic etching of sacrificial silicon-germanium layers with near-infinite selectivity to pure silicon channels.

Simultaneously, directional atomic layer etching techniques continue to evolve, offering damage-free material removal for sub-3nm nodes. Advanced plasma diagnostics, real-time optical emission spectroscopy, and data-driven process modeling are increasingly employed to maintain tight critical dimension control, ensuring high yield in next-generation semiconductor manufacturing.