HKMG Integration: Why Metal-Gate-Last Is Not Always High-k-Last

Does metal-gate-last also mean high-k-last?

No. Metal-gate-last identifies when the final metal electrode is formed; it does not uniquely identify when the high-k dielectric is formed. HKMG is a materials and device concept, while gate-first and gate-last describe integration choices. To interpret a real sequence, locate the dielectric, the temporary gate structure, source/drain processing and final metal replacement separately.

This distinction matters because each material experiences the steps that follow its formation. Moving final metal replacement later can reduce its exposure to earlier processing. A high-k dielectric already present earlier in the sequence still experiences that earlier thermal and chemical history. Integration comparisons must therefore specify which part of the stack is being protected. [P2]

Gate-first and replacement metal gate

In a gate-first approach, the functional gate stack is established before major subsequent source/drain processing. The completed stack must remain compatible with later thermal exposure and surrounding material changes. Interface reactions, charge and effective work function stability become important constraints.

Replacement metal gate uses a temporary structure during part of transistor formation, then creates the final metallic electrode in the space defined by removal of that structure. This retains a geometric reference while separating some early processing from final electrode formation. It introduces its own dependencies: exposing the temporary gate, removing the intended material selectively, preserving surrounding structures, and forming a continuous final electrode.

These are different integration problems, not a universal ranking of good and bad flows. Neither the words “gate-last” nor a node name prove that a particular process has a later dielectric deposition step. The actual module order is the evidence.

Read this Flow's dielectric and electrode separately

In the related 28nm Planar Flow overview, the GATE module contains high-k formation before the source/drain modules, while RMG appears later. The useful observation is the separation between early dielectric formation and later metal replacement. This teaching sequence should not be generalized to all planar CMOS or every process at that node.

A reader can trace three relationships: what has already been formed when high-k is introduced, which structures must survive the intermediate modules, and what the replacement operation changes. The overview supplies the module map. It does not promise unrestricted access to every detailed Step or show a manufacturing recipe.

Why the order changes the risks

A dielectric's electrical behavior depends on more than its nominal material. Interfacial changes and charge trapping can affect the completed device. Forming the dielectric earlier gives it a different history from forming it later, even if both finished stacks are called HKMG.

Replacement creates a confined geometry for later material formation. Continuous coverage and a connected electrode matter, but they are not identical to low resistance or the desired effective work function. An incomplete fill and an interface-related threshold shift are different failure mechanisms and should not be diagnosed as the same defect.

Later contact formation also has to preserve separation between conductive regions. A successful gate replacement does not by itself establish successful contact integration. Thinking in terms of dependencies makes these boundaries clearer than assigning every problem to “the gate stack.”

Connect the sequence back to device physics

The HKMG mechanism article separates dielectric capacitance, polysilicon depletion and effective work function. Use those distinctions when reading the Flow: ask which operation changes geometry, which establishes an interface and which supplies the final conductor.

The final stack, its process history and its measured electrical behavior are three related descriptions. Keeping them distinct prevents two common mistakes: treating metal-gate-last as proof that high-k was also deposited last, and treating a favorable dielectric capacitance as proof that all transistor leakage or reliability problems have been solved.