The source and drain are transistor terminals on either side of a gate-controlled channel. Extensions, raised regions and contacts can all contribute to how current reaches that channel. A production source/drain review treats junction and contact resistance as parts of the same electrical path .
What the Terminals Do
Under a given operating bias, carriers enter the channel through the source and leave through the drain. Resistance in the regions outside the gate-controlled channel can still limit current. The extension and contact therefore need separate attention rather than being treated as one ideal terminal .
Process map
A selected 4-step learning trail in 7nm FinFET
Locate the cavity prepared beside the spacer for later source/drain growth.
Real step names, layer-by-layer cross-sections, and rationale live inside the 7nm FinFET course, unlocked by account access.
How the Regions Are Formed
A source/drain region may be formed with implantation, selective growth and later activation, depending on the device architecture. The cited review compares extension and elevated-contact structures; it does not establish one sequence for every transistor .
The site's 7nm FinFET SD module makes this distinction visible. Its Spacer Etch and Cavity Etch prepares a p-side cavity, followed by eSiGe Growth. A separate eSi Growth step represents the n-side growth path; later a junction anneal follows the source/drain implants. These four approved steps in the current flow are linked as a sequence rather than a generic course directory.
Resistance, Strain and Leakage
The outside-channel path includes contributions from the junction region and its contact. Reducing one component may leave the other as the limiting resistance, so a completed device is needed to evaluate the intended improvement .
Some architectures use embedded material to strain the channel, while others prioritize a different junction and contact design. These choices are architecture-dependent and must be evaluated alongside leakage, series resistance and the off state .
Follow the Learning Route
Start at the cavity etch and ask which surface is exposed for later growth. At eSiGe Growth, distinguish the p-side stressor from the electrical terminal it helps form. Compare eSi Growth on the n-side, then follow the junction anneal step and ask what thermal processing changes after implantation. The article is public; the linked steps follow the 7nm Flow's access rules. For the neighboring concepts, see sidewall spacers, ion implantation and dopant activation.
References
Source/Drain Junctions and Contacts for 45 nm CMOS and Beyond
M. Ozturk, Jing Liu