Lightly Doped Drain (LDD): Physical Principles, Device Integration, and Technology Evolution

What LDD changes

A lightly doped drain (LDD) is a less heavily doped extension between a MOSFET channel and its heavily doped source/drain region. The extension spreads part of the drain-side potential drop, reducing the local electric-field peak and associated impact-ionization and hot-carrier stress in the device conditions studied by Ogura and colleagues [P1]. It also adds series resistance. “LDD” therefore names a device structure and a design trade-off, not a guarantee that every leakage or reliability metric improves.

The 40nm BSI image-sensor flow makes that structure easier to locate. Its NMOS LDD photo Step defines the implant opening; the next NMOS LDD implant Step places the extension in the process sequence. These two Steps give a manufacturing coordinate for the field-management idea. They do not specify a universal implant recipe or prove the electrical result of an individual device. Anonymous visitors see a limited Step preview; a free account can read the full Step text.

Field mechanism and its limit

The drain voltage is not dropped at a single mathematical point. A graded drain-side region changes how the potential is distributed along the channel edge. The original LDD device study compared conventional and LDD structures using device measurements and two-dimensional field simulations; it reported less concentrated drain-side field and reduced impact ionization for its tested geometry and bias [P1]. The mechanism depends on the extension profile, gate geometry and operating bias. A different stack or bias must be measured, not inferred from the acronym.

The extension can also reduce drive current when its resistance causes a larger voltage drop. The same study explicitly examined this series-resistance penalty [P1]. A useful comparison therefore asks for both the drain-side field or reliability outcome and the on-state current or resistance outcome. A lower peak field alone is an incomplete success criterion.

Where the extension enters a flow

After gate patterning, an extension implant can be placed close to the gate-defined channel. Later spacer formation separates the heavier source/drain region from that edge; activation and diffusion then affect the final profile. The order is a conceptual manufacturing sequence, while the linked 40nm pair shows only its named photo and LDD implant positions. Implant damage, activation and dopant movement are distinct results of subsequent thermal processing [T1]. The linked Steps do not expose a dose, thickness or thermal specification, and this article does not supply one.

The word “drain” emphasizes the high-field side under a particular operating polarity; a practical process may form source and drain extensions together. The relevant electrical gradient is the resulting profile after integration, not merely the presence of an implant named LDD.

What to check before transferring the idea

A planar NMOS example does not establish the same field distribution or resistance balance in every transistor architecture. Gate-all-around, FinFET and image-sensor pixels have different geometries and neighboring capacitances. Nor does the original LDD field result, by itself, establish a universal reduction in gate-induced drain leakage. Compare the actual device, bias and measured endpoint before extending the claim.

For the two-step manufacturing placement, open the linked 40nm Steps. For a definition and the field-versus-resistance trade-off, the explanation here may already answer the reader's question.