Controlling Surface Topography in Advanced BEOL: The Physics and Process Principles of Copper Dishing and Erosion

Introduction

In modern integrated circuit manufacturing, back-end-of-line (BEOL) metallization is responsible for routing electrical signals across billions of transistors. To minimize electrical resistance and mitigate electromigration, the semiconductor industry transitioned from subtractive aluminum etching to the copper dual damascene architecture. Because copper cannot be easily patterned via conventional reactive ion dry etching, trenches and vias are etched into the inter-metal dielectric, followed by thin barrier/seed layer deposition, electroplating fill, and surface removal via planarization.

Global surface planarization is achieved using chemical mechanical planarization (CMP). While CMP provides flatness across large wafer areas, it introduces surface topography variations known as copper dishing and dielectric erosion.

• Copper Dishing represents the height loss of the copper conductor relative to the adjacent patterned dielectric within a metal trench.
• Dielectric Erosion represents the localized thinning of the dielectric material between closely spaced metal lines relative to the unpatterned field dielectric area.

Controlling dishing and erosion is essential for yield and device reliability. Uncontrolled topography reduces the photolithographic depth of focus (DOF) in subsequent interconnect levels, creates sheet resistance variations, degrades breakdown characteristics, and leads to electrical shorts caused by residual metal stringers.

Physics & Mechanism

The physical mechanism of CMP combines contact mechanics, slurry fluid dynamics, and surface electrochemistry. Material removal relies on a synergistic chemical passivation and mechanical shear mechanism. Slurry oxidizers react with exposed copper to form a surface passivation layer, which is then removed by slurry abrasives and polishing pad asperities.

Mechanism of Copper Dishing

Copper dishing originates from differences in hardness and material removal rates between metallic copper and the surrounding dielectric. Ductile metallic copper exhibits lower hardness than silicon dioxide or low-k dielectric films. Consequently, under applied polishing downforce, the material removal rate of copper exceeds that of the surrounding dielectric.

During CMP, the polishing pad acts as an elastic, semi-rigid membrane. As it travels across the surface under downforce, the pad deforms and sags into softer, wide copper features. This localized deflection allows pad asperities and abrasive particles to continue abrading copper even after it reaches the height of the dielectric boundary. The deflection is geographically more severe in wider interconnect trenches, yielding a concave dishing profile where the line center suffers the greatest thickness loss.

Quantitatively, dishing is defined as:

Dishing = H_dielectric_pattern - H_Cu

where H_Cu is the height of the copper surface and H_dielectric_pattern is the height of the adjacent patterned dielectric.

Mechanism of Dielectric Erosion

While dishing is a feature-level defect within individual copper lines, dielectric erosion is a pattern-dependent array defect. Erosion occurs predominantly in regions with high pattern density and tight dielectric spacing.

In multi-step CMP integration, the initial step is Cu CMP where the Cu overburden is removed and preferably CMP is stopped on liner . From a contact mechanics standpoint, an elastic polishing pad cannot fully conform into narrow dielectric spaces between dense metal lines. Consequently, local contact pressure becomes concentrated on these narrow dielectric fins. Under elevated local pressure, mechanical wear of the dielectric accelerates dramatically.

Quantitatively, erosion is expressed as:

Erosion = H_dielectric_field - H_dielectric_pattern

where H_dielectric_field represents the unpatterned field dielectric height away from the dense interconnect array.

Process Principles

Mitigating dishing and erosion requires balancing contact pressure, pad elasticity, chemical passivation, and slurry selectivity.

Downforce and Pad Properties

According to classical wear kinetics, removal rate scales with pressure and velocity. In copper CMP, increasing downward pressure directionally increases pad sagging into copper lines, worsening dishing. Higher downforce also increases stress concentrations on narrow dielectric fins, accelerating erosion.

To counteract pad deformation, CMP processes employ high-rigidity pads or sub-pads that maintain global planarity. A rigid pad resists sagging into wide metal features. However, excessively rigid pads may suffer from poor wafer-scale conformity, leading to across-wafer non-uniformity. Thus, semi-rigid composite pads paired with in-situ pad conditioning are tuned to maintain local feature planarity alongside global uniformity.

Slurry Chemistry and Selectivity

Slurry formulation provides primary control over chemical dissolution and dynamic surface passivation. Typical copper CMP slurries contain:

1. Oxidizers: Form a passivation layer (such as copper oxide) on the surface.
2. Chelating Agents: Solubilize oxidized copper species to facilitate steady removal.
3. Corrosion Inhibitors: Adsorb onto copper surfaces to protect low-pressure recessed areas from static dissolution.

To prevent dishing in recessed areas, slurries display non-Prestonian removal behavior. In elevated topography regions, high mechanical shear disrupts the inhibitor film, driving high removal rates. In recessed trenches where contact pressure is low, the passivation film remains intact, suppressing static chemical dissolution.

Extended over-polishing times required to guarantee residue removal exacerbate dielectric thinning, where erosion increased steadily with increase in over-polish time . Multistep CMP schemes dynamically change slurry formulations between bulk copper overburden removal, barrier clearing, and final dielectric touch-up steps.

Challenges & Failure Modes

Failure to restrict dishing and erosion degrades circuit speed and long-term reliability.

Resistance and RC Delay

Dishing reduces the effective cross-sectional area of copper interconnect lines. Because resistance is inversely proportional to cross-sectional area, dishing increases sheet resistance. This resistance increase degrades signal propagation delay, particularly in wide global bus lines.

Dielectric Breakdown and Leakage

Erosion causes thinning of the inter-metal low-k dielectric between adjacent conductors. Under applied voltage, reduced spacing creates high electric fields, increasing leakage current and elevating susceptibility to time-dependent dielectric breakdown (TDDB).

Residual Metal Shorts

When overburden copper thickness varies across a die, complete clearing in low-density areas occurs before dense areas are fully cleared. Insufficient over-polishing leaves residual copper or barrier metal (such as Ta, TaN, or TiN) atop eroded dielectrics, causing inter-line electrical shorts. Extending over-polishing eliminates residues but increases dishing and erosion.

Technology Node Evolution

Managing surface topography has adapted to physical scaling and backend material changes.

Planar to FinFET Nodes

At mature nodes, dielectric materials (such as SiO2 or FSG) possessed high mechanical modulus, allowing higher CMP downforce. With the introduction of porous low-k and ultra-low-k (ULK) dielectrics in advanced nodes, low mechanical strength increased susceptibility to film cracking and delamination under shear stress.

To protect fragile dielectrics, process integration shifted to ultra-low downforce polishing combined with chemically dominant slurries. Furthermore, strict design-for-manufacturability (DFM) rules mandate inserting dummy metal fill patterns to achieve uniform pattern density across every die, distributing polishing pressure evenly.

Scaled Interconnect Scaling Challenges

As line dimensions drop below the electron mean free path of 36~40 nm at room temperature, electron scattering at surfaces and grain boundaries causes a rapid increase in copper resistivity [P1]. Managing topography variations becomes paramount because any cross-sectional loss from dishing amplifies this physical resistivity increase.

Related Integration Steps

CMP performance relies on tight integration with upstream and downstream operations across the back-end-of-line process flow.

• Lithography and Dry Etching: Patterning trenches via extreme ultraviolet lithography and anisotropic dry etching determines initial trench depth and sidewall profiles, directly influencing copper fill volume.
• Barrier and Seed Deposition: Conformally depositing thin liners via atomic layer deposition ensures interface adhesion and prevents copper diffusion into surrounding dielectrics.

Future Outlook

For sub-2nm nodes, alternative metals such as Ruthenium (Ru) and Cobalt (Co) are evaluated to replace copper in narrow lower-level interconnects due to superior resistance to electromigration and reduced thin-film size effects. From a planarization perspective, these harder metals offer greater mechanical resistance to pad deformation, widening the CMP process window.