What self-alignment contributes
A self-aligned contact uses an existing protective structure together with selective removal to help keep a contact opening from exposing a neighboring conductor. Lithography still places the opening. The protective cap or spacer provides an additional material boundary when the printed opening approaches the gate.
This is a relationship between geometry and material response. It does not eliminate overlay error, make a protective film immune to etching, or establish that every node uses the same contact integration. In the linked 14nm sequence, distinguish preparation of the hardmask, development of the dielectric opening, and conductor separation after metal filling.
Process checkpoint
Understand PECVD SiN Hardmask Deposition in context
Distinguish the hardmask from the developing contact opening, then inspect how CMP separates the filled contacts.
Process context for “Self-Aligned Contacts: Selective Etching, Protective Boundaries and Integration”: 14nm FinFET · CONTACT_SC · Step 165
Self-aligned contacts: from protected boundaries to conductionWhy the dielectric can clear while protection remains
Selective oxide etching depends on the balance between removal and surface inhibition on each exposed material. Fluorocarbon-plasma studies show that oxide and nitride can carry different inhibiting-film conditions and exhibit different removal rates. The balance depends on the substrate, incoming species and ion assistance; selectivity is a property of the complete process conditions, not an unconditional property of the material name.
The useful result is enough removal of the target dielectric while enough protection remains over the neighboring structure. More inhibition is not automatically better: a contact that does not clear is also a failure. Conversely, exposing a protective corner for too long can consume the boundary that was meant to isolate the gate. A structural drawing helps locate these competing boundaries; it cannot measure their remaining process margin.
Follow the linked 14nm sequence
Step 165 deposits the SiN hardmask. At that point the blanket layer is a future pattern carrier, not an open contact. Step 173 begins transferring the contact-trench pattern into the upper dielectric. Its shallow drawing should not be read as a completed path to the contact interface. Additional etch, cleaning and metallization operations occur before the tungsten-filled structure and CMP state at Step 194.
Ask a different question at each checkpoint: where will removal be allowed, how far has the opening developed, and has the metal overburden been removed so neighboring contacts are separated? A good result at one checkpoint does not establish the later results.
Separate electrical failures from their possible causes
Loss of gate protection can create an unintended contact-to-gate path after metallization. Incomplete opening, interface residue, poor metal coverage or voids can instead interrupt or restrict the intended conductive path. Contact resistance alone does not distinguish these causes; contact-chain diagnostics must be interpreted with structural and interface evidence.
Cleaning prepares the interface for the following operation, while filling establishes a conductor and CMP removes excess material above it. Calling all three “contact completion” hides the handoffs. Likewise, changing the conductor material alone cannot be assumed to repair a breached dielectric boundary or an incompletely cleared opening.
Opening is different from completion
The diagrams isolate two responsibilities: retain gate protection during removal, then separate conductors after filling. Lithography still sets the opening location. Protection is prepared earlier, and interface cleaning and metal formation occur between these conceptual states. The drawings cannot measure selectivity, remaining protection or contact resistance.
Independent concept schematic; not a course cross-section, measurement or process specification.
Related learning steps
References
Study of the SiO2-to-Si3N4 etch selectivity mechanism in inductively coupled fluorocarbon plasmas and a comparison with the SiO2-to-Si mechanism
M. Schaepkens, T. Standaert, N. R. Rueger, Pgm Patrick Sebel, G. Oehrlein, J. M. Cook
Silicon VLSI Technology - Full
James D. Plummer, Michael D. Deal, Peter B. Griffin
Silicon VLSI Technology · ISBN 978-0130850379