Introduction
In modern very-large-scale integration (VLSI) manufacturing, contact resistance ($R_c$) at the metal-semiconductor interface represents one of the most critical bottlenecks to overall device speed and power efficiency . As transistors scaled down from planar geometries to complex three-dimensional architectures like the fin field effect transistor, the physical contact area shrank dramatically . Consequently, reducing specific contact resistivity became paramount to sustain drive currents and prevent severe performance degradation [P4, T1].
Low energy contact (LEC) strategies refer to the integration of low-kinetic-energy process steps—including ultra-low energy ion implantation, mild plasma surface treatments, and low-damage metallization techniques—to form highly conductive, abrupt electrical interfaces with minimal damage to the underlying crystalline lattice [T1, P2]. By preventing damage to the delicate semiconductor junctions, these low-energy approaches facilitate hyper-abrupt doping profiles and minimize defect states, preserving the optimal band structure required for low-resistance carrier transport [P1, T2]. Understanding the fundamental physics of these processes is critical for engineers developing devices at advanced technology nodes, such as the 14nm FinFET and 7nm FinFET process flows .
Physics & Mechanism
The operation of a low energy contact is rooted in solid-state band theory and the physics of metal-semiconductor interfaces [P1, T2]. When a metal or a quasi-metallic contact material, such as titanium nitride (TiN), is brought into contact with a doped semiconductor, a Schottky barrier or an ohmic junction is established . The band structure of the semiconductor crystal is determined by the periodic potential of its lattice arrangement . The presence of impurities shifts the Fermi energy level relative to the conduction and valence band edges, modulating carrier concentrations according to Fermi-Dirac statistics .
At a metal-semiconductor interface, a mismatch in work functions leads to band bending and the formation of an energy barrier known as the Schottky barrier height (SBH) [P1, T2]. For carrier transport to occur, electrons or holes must traverse this barrier [P1, T3]. In weakly doped or highly damaged contacts, the dominant carrier transport mechanism is thermal emission, where carriers must acquire sufficient thermal energy to surmount the potential barrier [P1, T3]. This thermally activated mechanism is highly sensitive to temperature and barrier height, often leading to unacceptably high contact resistance in nanoscale devices .
To transition from high-resistance Schottky contacts to low-resistance ohmic contacts, low energy contact processing aims to minimize the barrier width and maximize field emission (tunneling) [T1, (Engineering Practice)]. By utilizing ultra-low energy implants, engineers can introduce extremely high active dopant concentrations directly at the silicon surface, which dramatically narrows the depletion region [T1, T4]. Under these conditions, the tunneling probability of carriers increases exponentially, allowing field emission to dominate over thermal emission .
Furthermore, preserving the crystalline periodicity is critical . High-energy physical processes disrupt the periodic lattice potential, creating a dense population of dangling bonds and interface states [P2, T2]. These localized defect states pin the Fermi level near the center of the bandgap, preventing the modulation of the Schottky barrier and giving rise to unwanted carrier trap-assisted transport, such as two-dimensional variable range hopping (2D-VRH) [P1, P2]. This hopping conduction severely degrades carrier mobility and increases reverse leakage currents [P2, T3]. Thus, deploying low energy processes preserves the pristine nature of the crystal structure, ensuring that the band offsets and carrier transmission coefficients remain optimized [P1, T2].
Process Principles
The successful fabrication of low energy contacts relies on controlling the kinetic energy and flux of processing species to directionally optimize the contact properties [T1, P2]. The primary process parameters—such as implant energy, acceleration voltage, plasma power, and thermal budget—must be carefully co-optimized to avoid deep lattice damage and unwanted dopant diffusion [T1, (Engineering Practice)].
First, in low-energy ion implantation, the extraction and drift kinetics of the dopant ions are governed by space-charge limitations . According to Child's Law, the space-charge-limited current density of an ion beam scales with the extraction voltage raised to the power of 1.5 . Consequently, lowering the ion energy to form ultra-shallow junctions naturally reduces the available beam current, which can severely limit throughput . To address this, modern implanters operate in specialized modes . In deceleration mode (decel-mode), ions are extracted at a higher energy to maximize beam current and then decelerated just before reaching the wafer target . However, this mode runs the risk of energy contamination, where charge exchange between ions and neutrals results in non-decelerated, high-energy neutral species that penetrate deeply into the substrate, degrading junction abruptness . To prevent this, advanced drift-mode implanters utilize optimized ion optics to transport and focus low-energy beams directly without deceleration, enabling highly controlled, ultra-shallow contact doping .
Second, during contact metallization, the deposition method must prevent energetic damage to the shallow contact region (Engineering Practice). Physical vapor deposition (PVD) techniques, such as sputtering, can introduce highly energetic metal atoms and ions that bombard the semiconductor surface, generating lattice defects and disrupting interface abruptness [P2, (Engineering Practice)]. Low energy contact methods instead rely on softer chemical processes, such as atomic layer deposition (ALD) or low-power chemical vapor deposition (CVD) [P3, (Engineering Practice)]. In ALD, self-limiting surface reactions occur at low thermal energies, building the contact metal layer atomic layer by atomic layer without high-energy physical bombardment (Engineering Practice).
Third, surface passivation layers play a vital role in protecting the contact area from subsequent high-energy steps . For instance, depositing an ultra-thin dielectric blocking layer (such as Al2O3) prior to a light-element plasma treatment (e .g., hydrogen plasma used to passivate or modify dopants) acts as a physical energy attenuator . This blocking layer reduces the kinetic impact and limits the excessive penetration of energetic radicals, preventing damage to the underlying semiconductor while still allowing chemical passivation to occur .
Finally, the thermal budget during post-contact annealing must be directionally minimized (Engineering Practice). High-temperature processing can trigger unwanted chemical reactions at the interface, such as the uncontrolled oxidation of metal contacts (e .g., TiN turning into titanium oxynitride (TiOxNy)), which alters the work function and increases the Schottky barrier height . Additionally, excessive thermal budgets cause dopants to diffuse away from the contact interface, decreasing the peak surface concentration and broadening the junction . Modern rapid thermal annealing (RTA) and millisecond laser annealing are deployed to activate dopants and form silicides within a tightly controlled temporal window, maximizing electrical activation while maintaining hyper-abrupt profiles .
Challenges & Failure Modes
Implementing low energy contacts presents major engineering challenges, and failing to manage the process window leads to distinct physical failure modes [T1, P2].
One primary failure mode is energy contamination in decel-mode ion implanters . If the pressure in the beamline is not kept ultra-low, charge-exchange collisions produce a fraction of high-energy neutral dopants . These neutrals do not experience the deceleration electric field and strike the wafer with their original, high extraction energy . This results in a deeper-than-expected doping tail, which leads to short-channel effects, high source-drain punch-through leakage, and a loss of gate control [T1, (Engineering Practice)].
Another critical challenge is lattice damage-induced leakage current . Even low-energy processes can introduce surface defects, dangling bonds, and vacancies [P2, T2]. If these defects are not completely annihilated during subsequent thermal steps, they act as trap states within the bandgap . Under reverse bias, these states facilitate carrier generation and hopping conduction (such as 2D-VRH), leading to high gate-to-source or drain-to-substrate leakage currents and premature off-state breakdown [P2, T3].
Furthermore, chemical instability at the contact interface represents a persistent reliability issue [P1, P3]. For instance, during the deposition of titanium nitride (TiN) barrier layers, trace amounts of oxygen can lead to the formation of TiOxNy . This oxidation modifies the interface band alignment, increasing the conduction band offset (CBO) and introducing a higher potential barrier for electron extraction . The resulting increase in Schottky barrier height reduces the drive current and dramatically lowers the fill factor of the device . Similarly, in stacked dielectric and metal structures, the diffusion of hydrogen or hydroxyl (OH) groups can lead to severe threshold voltage hysteresis and instability . If hydrogen species diffuse excessively into the channel, they can act as unwanted donors, causing unintentional channel doping and a complete loss of transistor switching behavior .
Lastly, specific contact resistance ($R_c$) degradation occurs if dopant activation is insufficient . At extremely low implant energies, a significant portion of the dopant dose is positioned very close to the surface, where it is highly susceptible to being lost to the overlying oxide capping layer or silicide during chemical reactions . If the peak surface active dopant concentration drops below the threshold needed for field emission, the contact reverts to a thermionic emission regime, resulting in an exponential increase in contact resistance [P1, T1].
Technology Node Evolution
The integration of low energy contact technology has undergone a dramatic transformation across successive logic nodes, directly tracking the evolution of transistor architectures (Engineering Practice).
At the planar 28nm planar flow, contacts were formed on flat silicon surfaces using nickel-platinum silicide (NiPtSi) (Engineering Practice). Low-energy ion implantation was primarily used to form ultra-shallow source/drain extensions, and standard decel-mode implanters were sufficient to maintain junction depths below the scaling limits . The contact area was relatively large, meaning that contact resistance did not yet dominate the overall parasitics (Engineering Practice). The 28nm node relied heavily on basic RTA to activate dopants and form stable silicides without severe risk of short-channel degradation .
As the industry transitioned to the 14nm FinFET node, the contact scheme had to adapt to a three-dimensional landscape (Engineering Practice). The narrow, vertical fins restricted the contact area, causing contact resistance to spike (Engineering Practice). To combat this, low energy contact (LEC) processes were introduced to selectively dope the vertical fin sidewalls without damaging the fragile, high-aspect-ratio silicon structures (Engineering Practice). Highly conformal, low-energy plasma doping and advanced co-implantation processes (using species like carbon to suppress dopant diffusion) were adopted to maintain abrupt junctions [T1, (Engineering Practice)].
At the 7nm FinFET node and beyond, the physical limits of silicide scaling were reached (Engineering Practice). Traditional silicides became too resistive due to thin-film agglomeration and carrier scattering at the interfaces . The industry transitioned to trench-contact metallization using low-energy atomic layer deposition of cobalt (Co) or ruthenium (Ru) direct contacts (Engineering Practice). The contact integration scheme shifted to a "contact-over-active-gate" (COAG) topology, where even a slight amount of process-induced damage could cause catastrophic shorting between the gate and the contact (Engineering Practice). To prevent this, extremely low-energy, highly selective dry etching processes and low-energy radical surface treatments were implemented to clean the contact trench bottoms without eroding the thin spacers or damaging the channel (Engineering Practice).
Related Processes
Low energy contact engineering does not exist in isolation; it is deeply intertwined with several key adjacent steps in the semiconductor fabrication sequence (Engineering Practice).
- Dry Etching: Before contact metallization can occur, contact vias or trenches must be opened through interlayer dielectrics (Engineering Practice). This process, using advanced dry etching techniques, must be highly selective to prevent punching through the thin, heavily-doped junction region . The etching chemistry and plasma power must be tuned to minimize physical sputtering damage at the trench bottom, ensuring a clean and low-defect surface for the subsequent contact [P2, (Engineering Practice)].
- Atomic Layer Deposition (ALD): Following the etch, highly conformal barrier layers and metal contacts must be deposited within high-aspect-ratio vias (Engineering Practice). Atomic layer deposition is the premier choice here because its self-limiting, low-energy chemical reactions provide excellent step coverage and prevent the substrate damage associated with physical sputtering [P1, (Engineering Practice)].
- Ion Implantation: Prior to metallization, the contact areas are subjected to pre-contact ion implantation to boost active carrier concentrations at the interface . Operating the implanters in low-energy drift modes is crucial to keep the dopants localized near the surface, enabling field-emission-dominated transport .
- Rapid Thermal Annealing (RTA): Once the contact dopants are implanted or the silicide metal is deposited, rapid thermal annealing is used to activate the dopants and complete the phase transformation of the contact silicide . This thermal step must be precisely controlled to avoid dopant deactivation and interfacial degradation [P1, (Engineering Practice)].
Future Outlook
As the semiconductor industry marches toward advanced architectures like nanosheet gate-all-around (GAA) transistors, forksheet field-effect transistors, and 3D complementary field-effect transistor (CFET) designs, low energy contact engineering will face even more stringent constraints .
One major area of research is the development of contacts for two-dimensional (2D) transition metal dichalcogenides (TMDs), such as molybdenum disulfide ($MoS_2$), which are being investigated as channel materials for extreme sub-nanometer nodes (Engineering Practice). These monolayer materials are incredibly fragile, and any conventional high-energy metallization process completely destroys their atomic structure, causing high contact resistance (Engineering Practice). Researchers are developing "van der Waals contacts" and low-energy physical transfer techniques to softly place metal layers onto the 2D sheets, preserving their intrinsic electronic properties (Engineering Practice).
Additionally, the use of low-work-function and high-work-function interlayer materials (such as ultra-thin oxides or nitrides) is being explored to eliminate Fermi level pinning . These metal-insulator-semiconductor (MIS) contact schemes rely on low-energy, atomic-scale deposition to insert a thin barrier that unpins the Fermi level, dramatically lowering the Schottky barrier height without requiring ultra-heavy doping [P1, (Engineering Practice)]. Finally, as device structures scale vertically, co-designing the low energy contact processes with advanced backside power delivery networks (BSPDN) will become essential, requiring low-energy contact formations from both the front and back sides of the silicon wafer .