Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
7nm FinFET Metal-Nine Interconnect Integration: ESL Chemistry, Damascene Logic, and Module Dependencies
Role in the Complete Flow The 7nm FinFET metal-nine (M9) interconnect integration module occupies a critical position in the back-end-of-line (BEOL) stack of a 7nm CMOS FinFET…
7nm FinFET Contact-Via Integration Process Flow: Principles, Mechanisms, and Module Dependencies
Role in the Complete Flow The 7nm FinFET contact-via integration module occupies a pivotal position in the overall process sequence: it bridges front-end-of-line (FEOL)…
Direct Bond Interconnect: Physics, Process Principles, and Integration in Advanced Semiconductor Packaging
Direct bond interconnect (DBI) is a planar, bumpless bonding technology that forms chip-to-chip or wafer-to-wafer electrical connections through simultaneous…
HKMG Explained: High-k Dielectrics, Metal Gates and EOT
Separate dielectric capacitance, polysilicon depletion and effective work function.
Low Energy Contact (LEC) in Semiconductor Manufacturing: Physics, Process Principles, and Advanced Node Evolution
As CMOS technology scales deeper into the nanometer regime, the resistance associated with the interface between metal interconnects and semiconductor source/drain regions—known…
Pre-Metal Dielectric (PMD): Physics, Process Integration, and Evolution Across Advanced Semiconductor Nodes
In the architecture of a modern integrated circuit, the transition from front-end-of-line (FEOL) transistor fabrication to back-end-of-line (BEOL) interconnect metallization…
Self-Aligned Contact (SAC) in Semiconductor Manufacturing: Principles, Physics, and Integration Logic
As semiconductor technology nodes scale below 28 nm, the pitch between transistor gates shrinks faster than the improvement in lithographic overlay control, creating a…
Mastering the Dual Work Function Metal Gate: Principles, Integration, and Advanced Node Evolution
Why do nFET and pFET gates need different effective work functions? Trace the p-side metal, selective mask and n-side metal in a 7nm FinFET flow.
First Via Level (V1): Linking Wiring Layers
The first via connects adjacent metal levels through dielectric. The 40nm flow verifies Via 1 patterning and etches, but the selected trail does not verify a specific fill metal.
Deep Dive into Local Via (V0) Integration: Principles, Physics, and Advanced Node Challenges
In modern integrated circuits, scaling transistor density requires severe reductions in device geometry and interconnect dimensions.
Guide to Gate Interconnect: Physics, Process Integration, and Nanoscale Evolution
In modern semiconductor manufacturing, the gate interconnect represents the critical physical and electrical bridge between the active transistor switching element and the upper…
Low Energy Contact Engineering: Principles, Physics, and Advanced Node Integration
In modern very-large-scale integration (VLSI) manufacturing, contact resistance ($R_c$) at the metal-semiconductor interface represents one of the primary bottlenecks to overall…