7nm FinFET Contact-Via Integration Process Flow: Principles, Mechanisms, and Module Dependencies

Role in the Complete Flow

The 7nm FinFET contact-via integration module occupies a pivotal position in the overall process sequence: it bridges the front-end-of-line (FEOL) transistor formation and the middle-of-line/back-end-of-line (MOL/BEOL) interconnect construction [P1]. When this module receives the wafer, the replacement metal gate (RMG) process has already finalized the high-k/metal gate (HKMG) stack, source/drain (S/D) epitaxy has been completed, and silicide contacts have been formed on the exposed S/D regions [P3]. The pre-metal dielectric (PMD) stack is either partially or fully deposited, providing the dielectric isolation matrix through which contact and via etch openings will be created [A1].

What this module must deliver downstream is a set of electrically functional, mechanically robust, and spatially precise vertical conduits connecting the transistor terminals to the first metal interconnect layer [A1]. At the 7nm node, the contact-via (VC) module is responsible for forming self-aligned contacts (SACs) that land on silicided S/D regions without shorting to the adjacent gate, as well as the subsequent via structures that connect those contacts to the metal-zero (M0) interconnect level [P2]. The module must also ensure that the PMD deposition provides adequate dielectric isolation, that etch selectivity preserves gate and fin integrity, and that the barrier/seed metallization achieves conformal coverage inside high-aspect-ratio features [P1].

The downstream consumer of the VC module is the 7nm FinFET metal-zero interconnect integration process flow, which expects a planarized top surface with exposed contact/via plugs ready for M0 trench patterning [P1]. Any non-uniformity, voiding, or residual contamination propagated from the VC module will directly degrade M0 resistance and yield [T1].

Entry State and Sequence Logic

Upstream Dependencies

When the wafer enters the VC module at 7nm FinFET, several critical features must already be in place [P3]. The fin structures have been patterned using self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP), followed by shallow trench isolation (STI) formation and fin reveal [P3]. The dummy gate has been patterned, spacers have been formed, and S/D epitaxy — SiGe for PMOS and Si:P or similar for NMOS — has been deposited to introduce strain and reduce external resistance [P1]. The RMG process has replaced the dummy gate with the HKMG stack, and silicidation has formed low-resistance contacts on the S/D regions [P2].

The PMD stack itself is typically a multi-sublayer structure, including a PMD liner (e.g., silicon dioxide or silicon oxynitride) (Engineering Practice), a PMD main layer, and a CMP cap layer [A1]. The liner serves as an etch stop and diffusion barrier, the main layer provides bulk dielectric isolation, and the cap layer serves as a polishing stop for chemical mechanical polish (CMP) planarization [P1]. The sequence logic demands that PMD deposition occur after silicidation but before contact patterning, because the PMD must encapsulate the transistor topography while leaving the silicide surfaces accessible for subsequent etch-back contact formation [A1].

Module-Internal Sequence

Within the VC module, the sequence follows a tightly coupled chain: PMD deposition and planarization, contact lithography using extreme ultraviolet (EUV) or multiple patterning, anisotropic dielectric etch with high selectivity to the silicide and gate materials, pre-metal clean, barrier/seed deposition, tungsten (W) or cobalt (Co) fill, and CMP planarization [T1]. Each step's output constrains the next: PMD uniformity determines etch depth control; lithography fidelity determines contact placement accuracy; etch selectivity determines whether the gate is damaged; and metallization conformality determines whether voids form inside the contact holes [P1].

At 7nm, EUV lithography is comprehensively applied to MOL contacts and minimum-pitch via interconnects, which simplifies the patterning sequence by reducing mask layers and improving critical dimension (CD) fidelity compared to immersion multiple patterning [P1]. This decision cascades through the entire VC module: fewer masks mean fewer alignment errors, tighter CD distributions, and improved contact resistance distributions [P1].

Physical and Chemical Mechanisms

PMD4 Deposition Integration Principles

The PMD deposition — particularly the fourth-generation PMD (PMD4) used in advanced 7nm FinFET flows — is governed by the need to fill high-aspect-ratio gaps between fins and gates without creating voids or seams [P1]. The deposition mechanism typically involves plasma-enhanced chemical vapor deposition (PECVD) or high-density plasma (HDP) deposition, where precursor gases decompose in a plasma environment and deposit silicon dioxide conformally over the three-dimensional fin/gate topography [A1]. The key physical principle is that gas-phase radicals must reach recessed regions between closely spaced fins before being depleted by surface reactions on exposed surfaces [P1]. If the sticking coefficient of the precursor is too high, deposition near the opening of the gap seals off the interior before full filling occurs, creating a seam void [A1].

HDP deposition addresses this by simultaneously depositing and sputtering: ions bombard the growing film surface, redepositing material from protruding regions into recessed areas, thereby improving gap fill [T3]. The balance between deposition and sputtering — the ratio of material addition to material removal — determines the conformality and void-free fill capability (Engineering Practice). At 7nm, the fin-to-fin spacing is extremely narrow, and the gate height relative to fin height creates complex topography that challenges even advanced HDP processes [P1].

Contact Etch Selectivity

The contact etch must penetrate the full PMD stack and stop precisely on the silicide layer without consuming the underlying silicon S/D or damaging the adjacent gate stack [T3]. This selectivity is achieved through a combination of plasma chemistry tuning and liner layer design [T3]. Fluorocarbon-based plasmas etch silicon dioxide preferentially over silicon nitride, so a silicon nitride liner deposited between the PMD main layer and the silicide serves as an etch stop [A1]. The chemical mechanism involves the formation of volatile silicon fluoride products ($\text{SiF}_4$) from the oxide, while the nitride forms a less volatile fluorinated surface layer that slows etching [T1].

At 7nm, the SAC architecture adds another layer of complexity: the contact must be self-aligned to the S/D region, meaning the gate spacer and an additional SAC liner (often silicon nitride) protect the gate sidewall from being exposed during contact etch [P2]. If the SAC liner is too thin, the etch may breach the gate sidewall and create a gate-to-contact short; if it is too thick, the contact opening narrows, increasing contact resistance [P1].

Barrier and Metallization Physics

Once the contact holes are opened, a barrier layer (typically titanium nitride, TiN) must be deposited conformally before the W or Co fill [T1]. The barrier prevents the diffusion of W fluorine precursors ($\text{WF}_6$) into the underlying silicon, which could cause a volatile reaction and device failure [T1]. The deposition mechanism for the barrier at 7nm typically uses atomic layer deposition (ALD), which provides self-limiting, layer-by-layer growth through sequential precursor exposure and purging cycles [P1]. ALD ensures conformal coverage even on the sidewalls of high-aspect-ratio contact holes, where conventional sputtering would suffer from poor step coverage [T1].

The metal fill itself — W or Co — is deposited by chemical vapor deposition (CVD), where precursor decomposition fills the contact hole from the bottom up [T1]. The physical mechanism governing fill quality is the competition between surface reaction kinetics and precursor diffusion into the feature [T3]. If the surface reaction is too fast relative to diffusion, the opening narrows prematurely, trapping a void inside (Engineering Practice). This is particularly critical at 7nm, where contact dimensions are so small that even minor process drift can cause incomplete fill [P1].

Contact Resistance Physics

The contact resistance at the silicide-to-barrier interface is governed by the Schottky barrier height and the carrier transport mechanism across that interface [P1]. At 7nm, the contact area is extremely small, so the specific interface resistance must be minimized through interface engineering: the silicide composition, the barrier work function, and any intermediate dopant segregation layers all interact to determine whether carrier transport is dominated by thermionic emission (high barrier) or by tunneling (low barrier, heavily doped interface) [P1]. The 7nm FinFET contact engineering achieves reduced contact resistance ($R_{\text{CNT}}$) through fourth-generation S/D epitaxy that raises the active dopant level at the silicide interface, thereby thinning the barrier and enabling tunneling-dominated transport [P1].

Interfaces and Failure Propagation

PMD-to-Silicide Interface

The PMD-to-silicide interface is the primary etch-stop boundary during contact formation [T1]. If the PMD deposition introduces contaminants (e.g., fluorine residues, moisture, or metallic impurities) (Engineering Practice) at this interface, the subsequent thermal cycles during barrier deposition and annealing can drive these contaminants into the silicide, degrading its phase integrity and increasing contact resistance [A1]. Conversely, if the silicide surface is not properly cleaned before PMD deposition, native oxide or residual photoresist can create an interfacial layer that blocks the etch stop function, leading to silicide punch-through [T1].

Gate-to-Contact Interface

The gate-to-contact interface is the most failure-sensitive boundary in the VC module (Engineering Practice). The SAC liner must maintain integrity throughout the contact etch; any pinhole or thinning creates a leakage path between the gate and the S/D contact, manifesting as elevated off-state current ($I_{\text{off}}$) or, in severe cases, a hard short [P2]. This failure propagates downstream: a gate-to-contact short is not repairable by subsequent process steps, so it directly impacts yield [P1]. At 7nm, the gate-to-contact spacing is at its minimum, and EUV lithography's improved fidelity is critical for preventing CD variation that would narrow this spacing further [P1].

Contact-to-M0 Interface

After CMP planarization, the top of the contact plug must be coplanar with the PMD cap surface so that the subsequent M0 trench etch can land uniformly [P1]. If CMP overpolishes the contacts, the contact recess reduces the cross-sectional area at the contact-to-M0 interface, increasing via resistance [P1]. If CMP underpolishes, residual W or barrier material on the PMD surface creates shorts between adjacent contacts [T1]. This directional tradeoff — between dishing (overpolish) and erosion (underpolish) — is governed by the selectivity of the CMP slurry to W versus the PMD dielectric (Engineering Practice).

Failure Propagation Summary

The directional logic of failure propagation in the VC module follows a clear hierarchy: upstream defects in fin/gate topography create PMD fill challenges $\rightarrow$ PMD fill defects cause etch depth non-uniformity $\rightarrow$ etch non-uniformity causes barrier coverage gaps $\rightarrow$ barrier gaps cause W fill voids or diffusion $\rightarrow$ W fill defects cause elevated contact resistance $\rightarrow$ elevated contact resistance degrades drive current ($I_{\text{on}}$) and delays the entire device performance window [P1]. Each stage's tolerance budget shrinks at 7nm, making cross-module co-optimization essential rather than optional [P1].

Walk the Real Module

To see how these principles translate into a concrete process sequence, we can walk through the actual 7nm FinFET contact-via integration steps [P1]. The interactive flow provides a step-by-step view of the VC module, where each step's inputs, actions, and outputs are documented in engineering detail (Engineering Practice).

The sequence begins with PMD liner deposition on the completed FEOL structure, followed by PMD main layer deposition with gap-fill optimization, CMP planarization to the cap layer, and then contact lithography and etch [T3]. At Step 335 in the interactive flow, the VC module process flow reaches a critical juncture where the PMD4 deposition and subsequent contact patterning converge — this is the point where deposition integration principles, etch selectivity, and barrier metallization all must align to produce a functional contact [T3].

For engineers studying the broader context, the 7nm FinFET process flow article provides the complete transistor-level sequence, while the 7nm FinFET contact integration process flow article dives deeper into the contact-specific physics [P2]. Together, these resources form a connected learning path from device architecture through contact formation to interconnect integration [A1].

The key takeaway from walking the real module is that the VC sequence is not a linear set of independent unit processes but a coupled chain where each step's process window is bounded by the upstream step's output quality and the downstream step's tolerance requirements (Engineering Practice). The 7nm node compresses all these tolerances to the point where statistical process control alone is insufficient; systematic co-optimization of lithography, etch, deposition, and CMP is required [P1].

Related Learning Paths

Engineers who want to deepen their understanding of the 7nm FinFET contact-via integration should explore the following adjacent topics:

1 [P1]. Contact integration physics: The 7nm FinFET contact integration process flow article expands on the Schottky barrier engineering, silicide formation, and SAC liner design that underpin the contact resistance optimization discussed here [P1].

2. Complete transistor flow: The 7nm FinFET process flow article covers the FEOL steps — fin patterning, gate stack formation, S/D epitaxy — that produce the entry state for the VC module [P1].

3. M0 interconnect integration: The 7nm FinFET metal-zero interconnect integration process flow article picks up where this VC module ends, detailing how the contact plugs interface with the first metal layer and the etch stop layer (ESL) deposition principles that govern that transition [P3].

4. Scaling theory and device physics: Understanding why the VC module's tolerances are so tight at 7nm requires grounding in MOSFET scaling laws, short-channel effect physics, and the parasitic resistance/capacitance budget that scales with gate length [T2]. The subthreshold current equation and its exponential dependence on gate voltage explain why even small contact leakage can dominate off-state power [T2].

Future Outlook

As the industry moves beyond 7nm FinFET toward gate-all-around (GAA) nanosheet architectures, the contact-via integration challenges will evolve rather than simplify [P2]. GAA structures introduce new topography — sheets suspended between source/drain regions — that creates even more complex gap-fill requirements for the PMD layer [P2]. The contact formation on nanosheet S/D regions will require new silicide processes and potentially new barrier metals, as the exposed S/D area changes from a planar fin top to a multi-sheet cross-section [A1].

Additionally, the trend toward cobalt (Co) and ruthenium (Ru) as alternative contact metals — replacing W for lower resistance at scaled dimensions — introduces new deposition chemistry and barrier requirements [P1]. The ALD/CVD processes for these metals are less mature than W, and the interface physics with silicides and barrier layers is an active research area [T1].

Another emerging direction is the use of buried power rails (BPR), which move the power delivery network below the transistor plane and fundamentally alter the contact-via architecture [A2]. In BPR schemes, the VC module must form contacts that reach below the substrate surface, requiring new etch chemistries and barrier deposition approaches that are not constrained by the current PMD-based flow [P3].

Finally, the continued adoption of EUV lithography at higher numerical aperture (NA) will further simplify the contact patterning sequence, but stochastic effects — line-edge roughness (LER), CD variation from photon shot noise — will become more prominent at the sub-7nm scale and will require new resist chemistries and process optimization strategies [P1].