7nm FinFET Contact-Via Integration Process Flow: Principles, Mechanisms, and Module Dependencies

Role in the Complete Flow

The 7nm FinFET contact-via integration module occupies a pivotal position in the overall process sequence: it bridges front-end-of-line (FEOL) transistor formation and middle-of-line/back-end-of-line (MOL/BEOL) interconnect construction. When this module receives the wafer, the replacement metal gate (RMG) process has finalized the high-k/metal gate (HKMG) stack, source/drain (S/D) epitaxy is complete, and silicide contacts are formed on exposed S/D regions. The pre-metal dielectric (PMD) stack is deposited to provide the dielectric isolation matrix through which contact and via etch openings are subsequently created.

What this module delivers downstream is a set of electrically functional, mechanically robust, and spatially precise vertical conduits connecting transistor terminals to the first metal interconnect layer. At the 7nm node, the contact-via (VC) module forms self-aligned contacts (SACs) that land on silicided S/D regions without shorting to adjacent gates, as well as subsequent via structures connecting those contacts to the metal-zero (M0) interconnect level. The module also ensures that PMD deposition provides adequate dielectric isolation, etch selectivity preserves gate and fin integrity, and barrier/seed metallization achieves conformal coverage inside high-aspect-ratio features.

The downstream consumer of the VC module is the 7nm FinFET metal-zero interconnect integration process flow, which expects a planarized top surface with exposed contact/via plugs ready for M0 trench patterning. Any non-uniformity, voiding, or residual contamination propagated from the VC module directly degrades M0 resistance and yield.

Entry State and Sequence Logic

Upstream Dependencies

When the wafer enters the VC module in a 7nm FinFET flow, several critical features are already in place. Fin structures have been patterned using self-aligned double patterning or quadruple patterning, followed by shallow trench isolation (STI) formation and fin reveal. Dummy gates are replaced by HKMG stacks via RMG processing, spacers are defined, and S/D epitaxy (SiGe for PMOS and Si:P for NMOS) introduces strain to lower external resistance. Silicidation establishes low-resistance contacts on S/D regions prior to dielectric encapsulation.

The PMD stack itself is a multi-layer structure, including a PMD liner (e.g., silicon dioxide or silicon oxynitride), a PMD main layer, and a CMP cap layer. The liner serves as an etch stop and diffusion barrier, the main layer provides bulk dielectric isolation, and the cap layer serves as a polishing stop for chemical mechanical planarization (CMP). Sequence logic demands that PMD deposition occur after silicidation but before contact patterning, encapsulating transistor topography while allowing subsequent contact etch-back to reach silicide surfaces.

Module-Internal Sequence

Within the VC module, the process chain comprises PMD deposition and planarization, contact lithography using extreme ultraviolet (EUV) or multiple patterning, anisotropic dielectric etch selective to silicide and gate materials, pre-metal cleaning, barrier/seed deposition, metal fill (W or Co), and CMP planarization. Each step constrains the next: PMD uniformity governs etch depth control; lithography fidelity determines contact placement; etch selectivity prevents gate damage; and barrier/fill conformality eliminates internal voids.

At the 7nm node, EUV lithography is applied to MOL contacts and minimum-pitch vias, simplifying patterning by reducing mask counts and improving critical dimension (CD) fidelity compared to immersion multi-patterning. Fewer masks translate to reduced overlay errors, tighter CD distributions, and narrower contact resistance variation.

Physical and Chemical Mechanisms

PMD4 Deposition Integration Principles

The PMD deposition—specifically the fourth-generation PMD (PMD4) deposited after resistor seal cap formation—must fill high-aspect-ratio recesses around contact and resistor structures without creating voids or seams. Deposition utilizes plasma-enhanced chemical vapor deposition (PECVD) or high-density plasma (HDP) CVD, where precursor gases decompose in a plasma to deposit silicon dioxide over 3D structures. Gas-phase radicals must diffuse into recessed regions around tightly spaced features before being consumed by surface reactions at feature entrances. High precursor sticking probability seals gap entrances prematurely, forming seam voids.

HDP deposition balances chemical vapor deposition with simultaneous ion sputtering: energetic ions re-sputter material from protruding corners into recessed trenches, suppressing void formation. At scaled pitches, gate height relative to surrounding topography creates aggressive geometry that demands strict kinetic control during dielectric fill.

Contact Etch Selectivity

Contact etch must penetrate the PMD dielectric stack and stop on the silicide layer without consuming underlying silicon S/D or eroding adjacent gate stacks. Selectivity relies on fluorocarbon plasma chemistry combined with an underlying dielectric liner (e.g., silicon nitride). Fluorocarbon plasmas generate volatile silicon tetrafluoride (SiF4) from oxide layers while building a protective fluoropolymer film on nitride surfaces that retards etching.

In SAC architectures, gate spacers and an insulating cap protect gate sidewalls during contact opening. If the protective liner is excessively eroded, contact etch breaches gate sidewalls, inducing gate-to-contact electrical shorts. Conversely, under-etching leaves dielectric residue that inflates contact resistance.

Barrier and Metallization Physics

Following contact hole patterning, a conformal barrier layer (typically TiN) is deposited prior to metal fill to prevent reaction between fluorinated metal precursors (e.g., WF6) and underlying silicon. To overcome step-coverage limitations in narrow contact features, atomic layer deposition (ALD) is utilized because ALD can result in extremely conformal coverage of very thin layers [T1]. Specifically, ALD titanium nitride barrier films synthesized from organometallic precursors demonstrate excellent step coverage [P1].

Comparing physical and chemical deposition methods in high-aspect-ratio openings reveals that chemical vapor deposition achieves higher bottom coverage than physical vapor deposition techniques such as ionized metal plasma [P4]. Once the barrier layer is established, CVD metal fill (W or Co) proceeds via precursor surface reaction. Fill quality depends on the ratio of surface reaction kinetics to precursor mass transport into the feature; fast surface reaction relative to diffusion closes feature tops prematurely, trapping central keyhole voids.

Contact Resistance Physics

Contact resistance at the silicide-to-barrier interface is governed by Schottky barrier height and carrier transport mechanisms. Because contact areas shrink dramatically at advanced nodes, specific interface resistivity must be reduced via heavy interface doping and silicide phase control. Transport shifts from thermionic emission over high potential barriers to field emission (tunneling) through narrowed space-charge regions, stabilizing low contact resistance (R_CNT).

Interfaces and Failure Propagation

PMD-to-Silicide Interface

The PMD-to-silicide interface forms the primary etch-stop boundary during contact etch. Contaminants at this interface (such as residual moisture or organic residues) cause incomplete silicide wetting, interface voiding, or elevated phase transformation temperatures during thermal processing. Incomplete surface pre-cleans allow native oxide to block uniform contact landing, triggering local silicide punch-through or contact open failures.

Gate-to-Contact Interface

The gate-to-contact spacing is among the most sensitive boundaries in middle-of-line integration. The SAC liner must maintain dielectric integrity during prolonged contact over-etch. Pinholes or localized liner thinning create direct leakage paths between gate metal and S/D contacts, increasing off-state leakage (I_off) or causing catastrophic gate shorts. Because gate-to-contact shorts cannot be repaired by subsequent processing, liner erosion directly impacts die yield.

Contact-to-M0 Interface

Following metal CMP, contact plugs must be coplanar with the surrounding PMD cap surface to allow uniform landing of M0 trench etching. CMP over-polishing causes plug dishing, reducing the contact cross-sectional area and elevating via interface resistance. Under-polishing leaves metal residue on the dielectric surface, causing line-to-line bridging shorts between adjacent contacts.

Failure Propagation Summary

Defects cascade directionally through the module: upstream topography non-uniformities generate PMD gap-fill seams -> seam voids accelerate local etch rates, causing non-uniform contact depths -> non-uniform contact depths lead to incomplete barrier coverage -> barrier gaps permit precursor attack or voiding during metal fill -> fill voids elevate interface resistance, degrading drive current (I_on) and circuit timing margins.

Walk the Real Module

To observe how these physical mechanisms operate in an integration sequence, consider the middle-of-line flow. At PMD4 Deposition in the interactive flow, dielectric fill establishes the insulating matrix prior to multi-pass contact lithography and etch.

Engineers evaluating cross-module dependencies should refer to the 7nm FinFET process flow for overall FEOL context, and the 7nm FinFET contact integration process flow for silicide and contact spacer mechanisms. These connected modules clarify how lithography, plasma etch, ALD barrier deposition, and CMP co-optimize device yield.

Related Learning Paths

Engineers expanding their domain knowledge should review these related topics:

1. Contact integration physics: The 7nm FinFET contact integration process flow details silicide formation, Schottky barrier engineering, and SAC spacer rules.
2. Complete transistor flow: The 7nm FinFET process flow details FEOL operations including fin formation, HKMG replacement gate processing, and S/D epitaxy.
3. M0 interconnect integration: The 7nm FinFET metal-zero interconnect integration process flow covers M0 trench patterning, dual-damascene metallization, and etch-stop layer mechanics.
4. Device physics and scaling: Understanding contact scaling requires analyzing MOSFET short-channel controls, parasitic series resistance components, and subthreshold leakage trade-offs.

Future Outlook

Transitioning from FinFETs to gate-all-around (GAA) nanosheet architectures alters middle-of-line constraints. Multi-bridge nanosheet channels demand conformal dielectric fill around suspended sheet ends, intensifying PMD gap-fill challenges. Contact metallization on GAA S/D regions must uniformize interface resistance over complex 3D surface profiles.

Alternative contact metals, such as cobalt (Co) and ruthenium (Ru), are replacing tungsten (W) to minimize plug resistance at scaled dimensions. These metals require low-temperature ALD processes and thin diffusion barriers to avoid interface degradation. Additionally, buried power rails (BPR) route power delivery networks below the active silicon plane, shifting contact integration from conventional top-down MOL structures to deep substrate contact vias.