Introduction
As semiconductor devices continue to scale to keep pace with Moore's law, conventional polycrystalline silicon gates have encountered critical physical limitations . Specifically, polysilicon gates suffer from the gate depletion effect and dopant penetration, which artificially increase the effective oxide thickness and degrade transistor drive capability , . To overcome these challenges, the semiconductor industry transitioned to high-k metal gate (HKMG) technology, replacing silicon dioxide with a high-permittivity dielectric and substituting polysilicon with metal gate electrodes , .
Within this framework, integrating a dual work function metal gate (also known as a dual metal gate or DMG) is essential for modern complementary metal-oxide-semiconductor (CMOS) manufacturing , . A DMG architecture utilizes distinct metal stacks with different work functions to separately optimize the threshold voltage of n-channel metal-oxide-semiconductor (NMOS) and p-channel metal-oxide-semiconductor (PMOS) transistors , . This optimization is critical for maintaining high drive current while suppressing off-state leakage as device dimensions shrink , .
Physics & Mechanism
The core physics of the dual work function metal gate rests on work function engineering to establish appropriate threshold voltages for both transistor types , . The threshold voltage ($V_T$) of a metal-oxide-semiconductor field-effect transistor (MOSFET) is directly modulated by the work function difference between the metal gate electrode and the semiconductor channel , . This relationship is governed by the classical threshold voltage equation:
$$V_T = \phi_{ms} - \frac{Q_{ox}}{C_{ox}} + 2\phi_F + \frac{\sqrt{2\varepsilon_s q N_A 2\phi_F}}{C_{ox}}$$
where $\phi_{ms}$ represents the metal-semiconductor work function difference, $Q_{ox}$ is the oxide charge, $C_{ox}$ is the gate capacitance, $\phi_F$ is the Fermi potential, $q$ is the electron charge, $\varepsilon_s$ is the semiconductor permittivity, and $N_A$ is the channel doping concentration .
In a standard CMOS circuit, the NMOS transistor requires a gate metal with a low work function near the conduction band edge of silicon, whereas the PMOS transistor requires a gate metal with a high work function near the valence band edge of silicon , . If a single metal gate were used for both devices, one of the transistors would suffer from an excessively high threshold voltage, degrading switching speed and increasing power consumption , .
The physical origin of the metal work function is determined by the Fermi level position relative to the vacuum level, which is further modulated by interface states and Fermi-level pinning when placed in contact with a high-k gate dielectric , . To achieve continuous and precise work function tuning, advanced integration schemes leverage alloying and solid-state diffusion kinetics . For instance, by combining metals of dissimilar work functions, such as hafnium and molybdenum, into a binary alloy, the effective work function can be adjusted continuously between the work functions of the constituent elements . This adjustment is driven by thermally activated solid-state interdiffusion, where the composition-weighted electronic density of states at the dielectric interface determines the final effective Fermi level .
In highly scaled or multi-gate devices, such as a cylindrical surrounding double-gate (CSDG) MOSFET, DMG structures can also be engineered laterally along the channel direction to optimize electrostatic control . By placing a lower work function metal near the source and a higher work function metal near the drain, a built-in lateral electric field gradient is created .
The electrostatic potential $\psi(r,z)$ in such cylindrical structures satisfies the two-dimensional Poisson equation :
$$\frac{1}{r}\frac{\partial}{\partial r}\left(r\frac{\partial \psi}{\partial r}\right) + \frac{\partial^2 \psi}{\partial z^2} = \frac{q N_A}{\varepsilon_s}$$
where $r$ is the radial distance and $z$ is the distance along the channel .
The resulting potential step prevents the drain voltage from modulating the source-side injection barrier, which significantly suppresses short-channel effects (SCEs), such as drain-induced barrier lowering (DIBL) and threshold voltage roll-off , . Consequently, the subthreshold swing (SS), which defines the gate voltage swing required to change the drain current by one order of magnitude, remains close to the ideal thermionic limit :
$$S = \eta \times 60\ \text{mV/dec} \quad (300,\text{K})$$
where $\eta$ is the subthreshold slope factor . By suppressing the scaling-induced increase of $\eta$, DMG technology preserves steep subthreshold characteristics and low off-state leakage , . Additionally, this configuration reduces the peak electric field near the drain, mitigating hot-carrier effects (HCEs) that would otherwise degrade long-term device reliability .
Process Principles
The fabrication of dual work function metal gates requires careful control of thin-film deposition, etching, and thermal budgets to target precise threshold voltages , . In a typical gate-first or gate-last integration flow, the effective work function is determined by several interacting process parameters .
First, the thickness ratio of the stacked metal layers directly dictates the final alloy composition and the resulting effective work function . In intermixing schemes where a low work function metal is deposited over a high work function metal, the thermal budget of subsequent annealing processes drives the interdiffusion of these species , . The solid-state diffusion of these metals follows Fick's laws of diffusion, where the diffusion flux is proportional to the concentration gradient and the temperature-dependent diffusion coefficient . At elevated temperatures, metal atoms migrate into the adjacent lattice, altering the local chemical potential and the work function at the dielectric interface .
A higher annealing temperature or longer duration increases the diffusion length, leading to a higher degree of intermixing at the gate dielectric interface and causing a directional shift in the effective work function , . However, the total metal thickness must be co-optimized with the thermal budget; thicker layers require higher thermal energy to achieve full intermixing, whereas excessively thin layers may fail to form a continuous, stable interface .
To protect the underlying delicate high-k dielectric during the selective patterning of the different metal layers, an ultra-thin metal buffer layer, such as tantalum nitride (TaN), is typically deposited first . This buffer layer acts as a chemical barrier and a diffusion block . The nitrogen content and density of this buffer layer directionally influence its barrier efficiency; higher nitrogen concentration generally improves chemical resistance but can alter the baseline work function of the stack (Engineering Practice).
In a gate-last or replacement metal gate (RMG) flow, the physical topography of the gates is finalized using chemical mechanical planarization (CMP) . The uniformity and final height of the metal gates after CMP are strongly influenced by the local pattern density and dummy gate design . Because different metals (such as tungsten fill vs (Engineering Practice). titanium nitride work function layers) exhibit different polish rates, regions with higher dummy gate density can suffer from local over-polishing or dishing if not balanced . Implementing dummy gates with optimized layout density helps homogenize the mechanical load during CMP, ensuring uniform gate height across the die .
Challenges & Failure Modes
The integration of dual work function metal gates introduces several complex physical and chemical failure modes that can severely impact yield and reliability , , .
One primary failure mode is the thermal instability of the metal-dielectric interface during high-temperature processing , . In gate-first integration schemes, the metal gate stack must withstand high-temperature source/drain activation annealing . Under these extreme thermal conditions, highly mobile metal species can penetrate through the thin buffer layer and diffuse into the gate dielectric . This metal penetration degrades the dielectric integrity, leading to a massive increase in gate leakage current and, in severe cases, premature dielectric breakdown .
Another challenge is the control of interfacial oxygen and chemical reactions at the high-k boundary (Engineering Practice). Some low work function metals are highly reactive and prone to oxidation . If oxygen scavengers or barrier layers fail, oxygen vacancies can form in the underlying high-k layer, shifting the threshold voltage away from the target and degrading carrier mobility due to increased remote charge scattering .
Process-induced damage during selective etching represents another significant risk , . To define the NMOS and PMOS gate regions, one of the deposited work function metals must be selectively removed from one side of the wafer while protecting the other . If the dry etching chemistry or wet chemical etchant lacks sufficient selectivity, it can erode the underlying ultra-thin gate dielectric, causing catastrophic gate leakage and reliability degradation . Furthermore, if the work function metal is not fully cleared from the isolation boundaries, such as the shallow trench isolation (STI) edges, parasitic leakage paths can form, resulting in STI edge leakage and poor device-to-device isolation .
Lastly, during the CMP step of gate-last integration, variations in the dummy gate pattern density can cause non-uniform gate heights . If the dummy structures are poorly optimized, localized over-polishing can lead to thin gate electrodes with high sheet resistance, whereas under-polishing can leave metal residues that cause short circuits between adjacent gates .
Technology Node Evolution
The implementation of dual work function metal gates has evolved significantly across technological generations to address scaling limitations and geometrical transitions , .
28nm Node: Planar HKMG
At the 28nm planar node, the industry successfully introduced HKMG integration, utilizing both gate-first and gate-last approaches to replace traditional polysilicon gates . For planar devices, the 28nm Planar Flow established the baseline for managing two distinct work function metal stacks on a flat substrate, primarily relying on selective wet etching of metal layers to define NMOS and PMOS regions .
14nm Node: The FinFET Transition
As scaling progressed to the 14nm node, the industry transitioned to three-dimensional architectures with the adoption of the 14nm FinFET . The non-planar, vertical fin geometry of FinFETs significantly increased the complexity of DMG integration (Engineering Practice). Depositing multiple conformal work function metal layers over high-aspect-ratio fins required the adoption of highly conformal atomic layer deposition (ALD) processes rather than physical vapor deposition (PVD) to prevent pinch-off and void formation in the narrow gate trenches . Additionally, the RMG process became the standard flow, where dummy polysilicon gates are removed and replaced with the final HKMG stack late in the fabrication process to minimize the thermal budget seen by the metal gate , (Engineering Practice).
7nm Node and Beyond: Multi-Vt Engineering
At the 7nm node and beyond, the integration challenges intensified as the physical space inside the gate trench narrowed further, limiting the physical thickness of the work function metal stacks , (Engineering Practice). To achieve multiple threshold voltages (ranging from ultra-low to standard $V_T$) on a single chip, engineers had to move beyond a simple binary DMG system to multi-work-function stacks . This required extremely precise control of thin-film etching and the introduction of advanced chemical-mechanical polishing schemes using complex dummy gate density designs to maintain local gate height uniformity across highly heterogeneous layouts .
Related Processes
The successful integration of a dual work function metal gate is highly dependent on several adjacent semiconductor fabrication steps .
- Deposition: High-aspect-ratio gate trenches in modern nodes rely heavily on atomic layer deposition (ALD) to deposit ultra-thin, highly uniform work function metals and barrier layers, ensuring conformal coverage over complex 3D structures .
- Lithography and Etching: Defining the distinct NMOS and PMOS gate regions requires advanced lithography techniques coupled with highly selective dry etching and wet etching chemistry to pattern the metal stacks without damaging the underlying high-k dielectric or active channels , .
- Annealing: Thermal processing, such as rapid thermal annealing (RTA), is used to drive precise solid-state interdiffusion in alloyed gate stacks and to cure interface defects, directly establishing the final effective work function , .
- Chemical Mechanical Planarization: In gate-last RMG flows, CMP is critical for removing excess metal overburden and defining the individual gate electrodes, with uniformity controlled by dummy gate layout designs .
Future Outlook
As the industry transitions from FinFETs to gate-all-around (GAA) nanosheet architectures, the constraints on dual work function metal gates will become even more severe , (Engineering Practice). Because the nanosheet channels are completely surrounded by the gate, the space between stacked nanosheets is extremely restricted (Engineering Practice). Thick multi-layer metal stacks will no longer fit within these sub-nanometer gaps, rendering traditional deposition and etching techniques for DMG difficult to implement .
To address this physical limitation, research is shifting toward dipole engineering (Engineering Practice). Instead of using thick metal stacks to adjust the work function, ultra-thin layers of oxides (such as lanthanum oxide or aluminum oxide) are deposited at the high-k/interfacial layer boundary to induce a microscopic dipole layer . These interface dipoles shift the effective band alignment, allowing precise threshold voltage tuning using a single, ultra-thin metal gate layer across both NMOS and PMOS devices . Additionally, the development of novel 2D materials and alternative metal alloys with inherently tunable work functions remains a key focus for sub-2nm technology nodes .