A dual work function metal gate gives the n-type and p-type transistors in a CMOS pair different effective gate work functions. Each finished gate stack aims at a suitable threshold response for its channel type. The dielectric, interfaces and later processing all contribute to that response .
Why CMOS Needs Two Gate Responses
The gate voltage must change the channel barrier enough to turn a transistor on while still allowing it to turn off. An nFET and a pFET respond to opposite carrier types, so their desired effective gate work functions differ. The metal's tabulated vacuum work function is only a starting point. Interface dipoles, charge and the neighboring high-k dielectric can move the effective value seen by the device. In an experimental HfO₂-based CMOS demonstration, several electrode choices produced dual gate responses, and electron mobility depended on the electrode, interface layer and subsequent processing even with nominally similar dielectric layers .
Process map
A selected 3-step learning trail in 7nm FinFET
Locate the p-work-function metal stage in the replacement-gate sequence.
Real step names, layer-by-layer cross-sections, and rationale live inside the 7nm FinFET course, unlocked by account access.
How a Flow Keeps the Roles Separate
A replacement-gate integration must put the p-side and n-side work-function-setting stacks in their intended locations without treating the entire wafer as one gate type. Selective patterning can retain or remove a film in designated regions before the other gate material is introduced. This is an integration principle, not a universal material sequence: the exact layers and order depend on the flow.
The site's 7nm FinFET learning flow offers a concrete trail: PWF1 TiN Deposition, Dual Metal Gate Mask Lithography, then NWF TiAlC-based Deposition in its RMG module. The names identify a p-work-function stage, the patterning that separates gate regions, and a later n-work-function stage. They are three approved current Steps; the article links this sequence rather than a generic Flow directory. The Step names describe this site's example, not a rule that every dual work function gate uses those materials.
Effective Work Function Is a Stack Property
The effective work function belongs to the finished gate stack. A measured metal value by itself cannot establish the transistor threshold: the adjacent dielectric and interfaces matter. The cited CMOS demonstration compared electrode choices in completed HfO₂-based stacks, so its results apply to those tested combinations .
A gate choice must be judged alongside threshold, drive current and interface behavior. The demonstration does not establish that arbitrary metal pairs will yield the same electrical response .
Follow the Learning Route
At PWF1 TiN Deposition, ask which gate population the film is meant to influence. At Dual Metal Gate Mask Lithography, locate the selective separation between the gate regions. At NWF TiAlC-based Deposition, compare the later n-side work-function role with the earlier p-side step. The Blog is public; the linked Step pages follow the 7nm Flow's account permissions. For the surrounding concepts, see work function, high-k metal gates and threshold voltage.
References
Dual work function metal gate CMOS using CVD metal electrodes
V. Narayanan, A. Callegari, F. Mcfeely, K. Nakamura, P. Jamison, S. Zafar et al. · Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.