What does HKMG mean?
High-k metal gate (HKMG) combines a gate dielectric with a relatively high dielectric constant and a metallic gate electrode. The dielectric supports electrostatic coupling between gate and channel while limiting conduction through the gate stack. The electrode supplies the gate potential. Replacing the dielectric and replacing the electrode address related but distinct limitations of a conventional silicon-dioxide/polysilicon stack.
High-k can provide a given dielectric capacitance with a physically thicker insulating layer. A metal electrode removes the polysilicon depletion contribution and provides another way to establish the gate's effective work function. Neither change alone guarantees low total leakage, a particular threshold voltage or a reliable transistor.
Process map
28nm Planar Flow
Locate gate formation and metal replacement in the 28nm overview, keeping electrical function distinct from process order.
Electrical thickness differs from physical thickness
For an ideal dielectric layer, capacitance per area increases with permittivity and decreases with physical thickness. Equivalent oxide thickness, or EOT, expresses that capacitance as the thickness of an equivalent silicon-dioxide layer. It is a comparison of electrical behavior, not a direct measurement of the physical stack.
An interfacial dielectric contributes in series with the high-k layer. Improving the bulk high-k material therefore cannot remove the electrical contribution of an interfacial layer. Real measured gate capacitance can also reflect electrode and channel effects, so the ideal dielectric comparison must not be treated as a complete transistor model.
A physically thicker barrier can reduce direct tunneling under suitable band alignment, but leakage also depends on barrier properties and defects. Traps can provide additional conduction paths. The statement “higher k means lower leakage” is incomplete unless the comparison specifies capacitance, interfaces and the relevant leakage mechanism.
Why change the electrode too?
Polysilicon is a semiconductor. Under appropriate bias, a depleted region near its dielectric interface adds a series electrical contribution that weakens gate coupling. A metallic electrode avoids that particular depletion mechanism. This does not remove all series or quantum contributions to measured capacitance.
The effective work function helps set the relationship between gate voltage and channel charge. It depends on the gate material and its interfaces, rather than only a tabulated value for an isolated metal. Interface dipoles, fixed charge and trapped charge also influence electrical behavior. Consequently, threshold voltage cannot be inferred from the dielectric constant or metal name alone.
What HKMG does not solve by itself
Gate leakage and off-state source-to-drain leakage are different current paths. Improving the gate dielectric does not by itself eliminate drain-induced barrier lowering or other short-channel effects. Channel geometry and electrostatics remain important.
Reliability is also distinct from an initial capacitance measurement. Charge trapping can change threshold voltage over time, while interfaces and defects affect transport in the channel. A favorable initial EOT cannot establish long-term stability. It is useful to keep capacitance, leakage, mobility and variability as separate questions before examining their interactions.
From materials to a real sequence
HKMG describes the final gate stack, not a unique process order. Gate-first and replacement-metal-gate approaches expose different parts of that stack to different histories. Even within metal-gate-last integration, the high-k dielectric can be formed earlier or later depending on the chosen sequence.
The HKMG integration article explains how to distinguish those cases. The related Flow overview is useful for locating gate formation relative to source/drain and replacement modules. It does not substitute for this electrical explanation, and a technology-node label alone does not prove that every implementation uses the same gate stack.
References
The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies
H. Tseng