Introduction
In modern complementary metal-oxide-semiconductor (CMOS) scaling, maintaining electrostatic control while minimizing parasitic resistance is one of the most critical challenges faced by device physicists and process engineers . As the physical dimensions of transistors shrink, the parasitic resistance in the source and drain regions scales inversely with the contact area, severely limiting the drive current of the transistor , . Historically, planar devices relied on simple ion implantation and subsequent thermal annealing to form shallow junctions , . However, these conventional junctions suffer from high sheet resistance and poor short-channel immunity at advanced dimensions , .
To address these limitations, modern semiconductor manufacturing utilizes a process known as source drain recess (SDR) engineering . At its core, source drain recess is a process wherein the silicon substrate in the active areas adjacent to the gate electrode is selectively etched to create localized cavities or recesses , . These recessed regions are subsequently refilled using selective epitaxial growth (SEG) of highly doped semiconductor alloys, such as silicon-germanium (SiGe) for p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) or silicon-carbon (SiC) for n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) , .
This architectural shift achieves two primary engineering objectives (Engineering Practice). First, it enables the integration of strain-inducing stressors directly adjacent to the channel, boosting carrier mobility through band engineering . Second, it allows process engineers to implement raised source/drain structures, which significantly increase the contact volume and permit the formation of low-resistance self-aligned silicide contacts without risking junction consumption or excessive leakage , . Understanding the physical, chemical, and structural principles of the silicon recess etch is therefore foundational to mastering advanced front-end-of-line (FEOL) integration .
Physics & Mechanism
Lattice Strain Physics and Mobility Enhancement
The integration of a recess in the source and drain regions is primarily driven by the physics of uniaxial lattice strain . For an NMOS device, introducing carbon into the silicon lattice in the recessed regions creates localized tensile strain . Because the covalent radius of carbon is significantly smaller than that of silicon, the selective epitaxy of a silicon-carbon (SiC) alloy in the recessed source/drain regions induces lateral tensile strain ($\varepsilon_x$) and vertical compressive strain ($\varepsilon_z$) within the silicon channel . This strain tensor is quantitatively defined relative to the reference lattice constants :
$$\varepsilon_x = \frac{a_x - a_{x,ref}}{a_{x,ref}}, \quad \varepsilon_z = \frac{a_z - a_{z,ref}}{a_{z,ref}}$$
This strain breaks the six-fold degeneracy of the silicon conduction band, splitting the $\Delta_6$ valleys into lower-energy twofold degenerate $\Delta_2$ valleys and higher-energy fourfold degenerate $\Delta_4$ valleys (Engineering Practice). Electrons preferentially populate the lower-energy $\Delta_2$ valleys, which exhibit a lower longitudinal effective mass in the transport direction, thereby suppressing intervalley phonon scattering and enhancing electron surface mobility ($\mu_{ns}$) , .
The linear-region drain-source current ($I_{ds}$) in a MOSFET highlights how surface mobility directly translates to drive capability :
$$I_{ds} = \frac{W}{L} Q_{inv} , \mu_{ns} , V_{ds}$$
Here, $Q_{inv}$ represents the inversion-layer sheet charge density, while $W$ and $L$ represent the channel width and length, respectively . Under strong perpendicular electric fields, carrier transport is limited by surface scattering, which is modeled using the average perpendicular field ($E_{avg}$) in the inversion layer :
$$E_{avg} = \frac{E_b + E_t}{2}$$
where $E_b$ and $E_t$ are the perpendicular fields at the bottom and top of the inversion layer, respectively . By engineering uniaxial strain via recess stressors, engineers mitigate this surface scattering, boosting the effective drive current of advanced short-channel devices , .
Chemical Reaction Principles of Recess Etching
The creation of the recess cavity is accomplished via highly selective reactive ion etching (RIE) or dry chemical etching, often combined with wet chemical treatments to manage surface damage , . Silicon recess etch chemistries typically leverage halogen-based plasmas (such as fluorine, chlorine, or bromine) . The chemical mechanism relies on the adsorption of reactive halogen radicals onto the silicon surface, followed by ion-bombardment-induced desorption of volatile silicon tetrahalides (e .g., $\text{SiF}_4$, $\text{SiCl}_4$) (Engineering Practice).
During the over-etch phase of polysilicon gate patterning, an unintended silicon recess can occur due to plasma oxidation . In the presence of oxygen-containing plasmas (e .g., $\text{HBr}/\text{O}_2$), reactive oxygen species penetrate the ultrathin gate oxide under ion bombardment, reacting with the underlying silicon substrate to form a thin plasma-grown oxide layer . This oxidation process follows a modified Deal–Grove linear–parabolic growth relationship :
$$x = \left[ \frac{A}{2} + \sqrt{ \left( \frac{A}{2} \right)^2 + B (t + \tau)} \right]$$
In this model, $x$ represents the oxide thickness, $t$ is the oxidation time, and $\tau$ accounts for the initial oxide layer . The parameter $A$ is defined by the effective diffusion coefficient ($D$) and the interface reaction rate constant ($k$) :
$$A = \frac{2D}{k}$$
In low-temperature plasma environments, this oxidation exhibits an extremely low apparent activation energy (~0.02 eV), demonstrating that it is driven by ion-assisted kinetics rather than pure thermal diffusion . Subsequent wet cleaning steps using dilute hydrofluoric acid remove this plasma-grown oxide, leaving behind an undesirable recess in the active silicon area adjacent to the gate .
Alternative Carrier Modulation and Gate Recess Physics
While source drain recess is primarily a CMOS-centric process, analogous recess techniques are employed in high-frequency compound semiconductor devices, such as high electron mobility transistors (HEMTs) and pseudomorphic HEMTs (PHEMTs) . In these devices, a multi-step gate recess etch is used to define the gate foot and control the threshold voltage by thin-down of the barrier layer above the two-dimensional electron gas (2DEG) channel .
The process uses a dielectric (e (Engineering Practice).g., $\text{SiN}x$) as a hard mask to define the gate morphology, reducing parasitic capacitances ($C{gs}$ and $C_{gd}$) and enhancing the cutoff frequency ($f_T$) . The gate recessing often combines selective dry etching (using gases like $\text{BCl}_3/\text{SF}_6$ to selectively remove GaAs over AlGaAs) and wet chemical polishing (using diluted $\text{H}_3\text{PO}_4:\text{H}_2\text{O}_2:\text{H}_2\text{O}$ mixtures) to eliminate plasma-induced surface damage and achieve high channel current uniformity .
Process Principles
Designing a robust source drain recess process requires precise balancing of several chemical and physical parameters . These parameters interact directionally to govern the geometry, uniformity, and defect density of the resulting recess cavity .
[RF Bias Power] ──> Increases Ion Energy ──> Enhances Anisotropy ──> Deepens Recess Bottom
[Gas Chemistry (F/Cl/Br)] ─────────────────> Modulates Isotropics ─> Controls Lateral Undercut
[Wet Etch (TMAH/NH4OH)] ───────────────────> Crystallographic ─────> Forms Sigma-Shape (111)
Dry Etch Parameter Interactions
- Ion Energy and RF Bias Power: Increasing the radio frequency (RF) bias power shifts the etch regime toward physical sputtering, enhancing directional vertical etching . Higher bias power increases the vertical recess depth but can lead to severe lattice damage at the bottom of the cavity, which must be addressed prior to selective epitaxy , (Engineering Practice).
- Radical-to-Ion Flux Ratio: Modulating the source power relative to the bias power changes the ratio of neutral chemical radicals to active bombarding ions (Engineering Practice). A higher chemical radical flux (e (Engineering Practice).g., high fluorine concentration) promotes isotropic etching, leading to lateral undercutting of the gate spacer , (Engineering Practice). Conversely, halogen mixtures containing bromine (e (Engineering Practice).g., $\text{HBr}$) promote sidewall passivation, yielding vertical, anisotropic profiles (Engineering Practice).
Profile Engineering (U-Shape vs (Engineering Practice). Sigma-Shape)
- Anisotropic Dry Etch (U-Shape): Standard RIE processes produce a U-shaped recess cavity with rounded corners . This profile is optimized by adjusting polymerizing gas additions (such as $\text{CH}_2\text{F}_2$ or $\text{N}_2$) to deposit protective liners on the spacer sidewalls, preventing lateral erosion while allowing the bottom of the trench to be etched vertically .
- Crystallographic Wet Etch (Sigma-Shape): For advanced PMOS devices, process engineers transition from a dry etch to an alkaline wet etch (using solutions such as tetramethylammonium hydroxide (TMAH) or ammonium hydroxide) after the initial dry recess . These chemistries exhibit extreme selectivity toward specific silicon crystallographic planes, etching the ${100}$ and ${110}$ planes at orders of magnitude higher rates than the ${111}$ planes (Engineering Practice). This anisotropic selectivity naturally terminates the etch at the slow-etching ${111}$ planes, creating a highly precise Sigma-shape ($\Sigma$-shape) cavity , (Engineering Practice). The tip of the Sigma profile extends laterally beneath the gate spacer, positioning the subsequent SiGe stressor closer to the channel to maximize strain transfer efficiency , .
Multi-Step Etch Strategies
To achieve both structural precision and low defect density, advanced nodes implement multi-stage etching schemes , . An initial anisotropic dry etch defines the macro-depth of the cavity, followed by a highly selective, low-energy dry or wet "trim" etch , . This secondary step removes the surface layer damaged by high-energy ion bombardment, ensuring a clean, crystalline interface for the subsequent epitaxial growth , .
Challenges & Failure Modes
The execution of a sub-nanometer source drain recess is highly sensitive to process variations . Small deviations in etch kinetics or passivation layers can lead to catastrophic electrical failures .
Profile Control and Cavity Corner Rounding
During the fabrication of gate-all-around (GAA) nanosheet transistors, a horizontal recess of sacrificial silicon-germanium layers is required to form cavities for the inner spacers , . A common failure mode is corner rounding of these cavities due to diffusion-limited transport of etchants in high aspect ratio spaces .
If the cavity profile is not highly orthogonal, the subsequent deposition of the inner spacer dielectric will be non-uniform . Thin regions near the rounded corners can suffer from local dielectric breakthrough during the subsequent replacement dummy gate etch . This results in direct shorting between the metal gate stack and the epitaxial source/drain regions .
To prevent this, multi-stage etching processes are implemented where a primary lateral recess is followed by an inner trim etch to square off the cavity corners .
Rounded Cavity (Risk of spacer thinning & gate-S/D shorting):
[Gate]
[Spacer] ( ) <── Rounded cavity profile
[Channel]
Orthogonal Cavity (Uniform spacer deposition & robust isolation):
[Gate]
[Spacer] [ ] <── Squared-off profile via trim etch
[Channel]
Active Silicon Area Recess and Plasma-Induced Damage
During the main polysilicon gate over-etch step, plasma-induced oxidation of the silicon substrate can occur . Reactive oxygen ions cross the ultrathin gate oxide, forming an interstitial oxide phase that consumes the active silicon . When these oxides are removed in subsequent wet cleaning steps, a recess is formed in the source/drain extensions . This recess reduces the electrostatic control of the gate over the channel, increasing short-channel effects and degrading transistor drive current .
Furthermore, high-energy ion bombardment during dry etching creates a damaged amorphized silicon layer at the bottom of the recess, which can lead to high junction leakage and localized dislocation defects during epitaxial growth , (Engineering Practice).
Ion Channeling in Recessed Substrates
When ion implantation is performed directly into a recessed silicon cavity to dope the source/drain junctions, the crystalline nature of the exposed silicon substrate can lead to channeling . Ion channeling occurs when implanted dopants align with major crystallographic directions (such as the $[110]$ axis) and travel deep into the substrate without undergoing sufficient decelerating nuclear collisions . This broadens the dopant profile and increases the junction depth, which degrades short-channel immunity , .
To mitigate this, a thin amorphous screen oxide is grown or deposited at the bottom of the recess to randomize the trajectory of the incoming ions, ensuring shallow, well-controlled junctions .
Technology Node Evolution
The physical configuration and role of the source drain recess have evolved fundamentally across major technology nodes to meet the scaling demands of Moore's Law .
Planar (28nm) FinFET (14nm/7nm) GAA Nanosheet (Beyond 2nm)
[Gate] ___[Gate]___ === [Channel] ===
───┴─── │ ┌───┐ │ ─┬─ [Spacer] ─┬─
░░░░░░░░░ ░░░ │ │ ░░░ [S/D] [S/D]
(Flat S/D) (Fin Recess) (Dielectric Isolation)
28nm Planar Node
At the 28nm Planar Flow, the source drain recess was primarily introduced to integrate embedded SiGe (eSiGe) stressors for PMOS transistors , (Engineering Practice). The recess was a shallow, two-dimensional cavity formed using a self-aligned approach relative to the gate spacer , .
The primary challenge was managing the lateral undercut to prevent the growing SiGe from getting too close to the channel, which would cause short-circuit leakage, while keeping it close enough to maximize the compressive stress . Doping was typically introduced via high-dose ion implantation followed by rapid thermal annealing (RTA) , .
14nm to 7nm FinFET Nodes
As the industry transitioned to 3D architectures, such as the 14nm FinFET and 7nm FinFET nodes, recess engineering became three-dimensional . Instead of etching a flat substrate, process engineers had to etch three-dimensional silicon fins (fin recess) .
The fin recess etch must remove the top portion of the fin without eroding the shallow trench isolation (STI) oxide or damaging the ultra-thin gate spacers . In the 7nm FinFET node, highly selective crystallographic etching was introduced to create precise, merged Sigma-shaped cavities across multiple parallel fins , (Engineering Practice). This ensured that the epitaxially grown SiGe or SiC stressors could merge uniformly, minimizing void formation and optimizing uniaxial strain , , (Engineering Practice).
GAA Nanosheets and Beyond (Sub-2nm Nodes)
In gate-all-around nanosheet architectures, the traditional fin is replaced by a vertical stack of alternating sacrificial SiGe layers and silicon channel nanosheets , . The source drain recess process in GAA involves two distinct steps: 1 (Engineering Practice). Vertical Nanosheet Stack Etch: A highly directional anisotropic dry etch that cuts through the entire Si/SiGe stack to define the vertical boundaries of the source/drain regions . 2. Lateral Sacrificial Layer Recess: A highly isotropic dry chemical etch that selectively recesses the sacrificial SiGe layers horizontally relative to the silicon channel layers, creating cavities for the inner spacers , .
At these advanced geometries, ensuring that the source/drain epitaxial features do not leak into the underlying substrate is critical . This has led to the introduction of a dielectric isolation layer at the very bottom of the source/drain recess trench, decoupling the epitaxial source/drain regions from the underlying lower fin elements and suppressing parasitic sub-fin leakage paths .
Related Processes
The source drain recess does not exist in isolation; it is a critical link in a tightly integrated sequence of front-end processes .
[S/D Recess Etch] ──> [Pre-Epi Wet Clean] ──> [Selective Epitaxy (SEG)] ──> [Salicide Contact]
Selective Epitaxial Growth (SEG)
The recess cavity is designed specifically to host the subsequent selective epitaxial growth of SiGe, SiC, or highly doped Si , . The shape, depth, and surface cleanliness of the recess directly determine the crystal quality of the epitaxial layer , .
Any residual amorphized silicon, dry etch polymer, or native oxide at the bottom of the recess will cause crystallographic defects, such as threading dislocations or stacking faults, which degrade carrier mobility and increase junction leakage .
Advanced Wet Cleaning
Immediately following the recess etch and prior to epitaxial growth, wafers undergo critical wet cleaning steps (Engineering Practice). These cleans typically utilize dilute hydrofluoric acid to remove native oxides and restore a hydrogen-terminated silicon surface, preventing oxidation before the wafer enters the epitaxy chamber .
In some cases, specialized organic or polymer strip chemistries are used to remove halogenated carbon residues left behind by the RIE process without etching the sensitive gate spacer dielectrics (Engineering Practice).
Self-Aligned Silicide (Salicide) Contact Formation
Following selective epitaxy, the source and drain regions are metallized to form low-resistance contacts , . This process, known as self-aligned silicide or salicide, involves depositing a transition metal (such as nickel or cobalt) and performing a thermal anneal to react the metal with the underlying silicon or silicon alloy , .
The depth and profile of the original source drain recess must be optimized to ensure that the silicide reaction does not consume too much of the shallow junction, which would lead to junction penetration and high contact-to-substrate leakage , . The introduction of nickel silicide technology has been crucial in maintaining thin, highly conductive contact layers on recessed and raised source/drain architectures , .
Future Outlook
As scaling approaches the atomic limit, source drain recess technology is evolving toward atomic-level precision and complex 3D integration .
Atomic Layer Etching (ALE)
To overcome the physical limitations of conventional reactive ion etching—such as aspect ratio dependent etching (ARDE) and plasma damage—the industry is transitioning toward atomic layer etching (ALE) (Engineering Practice). ALE decouple the etch process into sequential, self-limiting surface modification and desorption steps .
By utilizing ALE for the silicon recess, process engineers can achieve sub-nanometer depth control with zero plasma-induced damage, ensuring pristine crystalline surfaces for subsequent epitaxy , (Engineering Practice).
Complementary FET (CFET) Integration
The next major architectural transition beyond GAA nanosheets is the complementary field-effect transistor (CFET), where n-type and p-type nanosheet transistors are stacked directly on top of each other (Engineering Practice).
This extremely dense 3D integration presents unprecedented challenges for the source drain recess process, requiring high aspect ratio etches that can selectively recess different materials at different vertical levels of the stack . Process engineers must develop multi-level recess and isolation schemes to allow separate, vertically stacked n-type and p-type selective epitaxy processes within the same active cell .
Alternative High-Mobility Channel Materials
The potential transition from silicon channels to alternative high-mobility materials, such as germanium (Ge) or III-V compound semiconductors (e .g., InGaAs), requires entirely new recess chemistry development , (Engineering Practice).
Because these materials possess lower surface bonding energies than silicon, they are highly sensitive to thermal and plasma-induced degradation . The recess processes for these materials must operate at lower temperatures and utilize highly selective chemical dry etches to prevent stoichiometry modification and defect generation , (Engineering Practice).