Deep Dive into Source Drain Recess: Physical Principles, Process Mechanisms, and Advanced Node Integration

Introduction

In modern complementary metal-oxide-semiconductor (CMOS) scaling, maintaining electrostatic control while minimizing parasitic resistance is one of the most critical challenges faced by device physicists and process engineers. As the physical dimensions of transistors shrink, the parasitic resistance in the source and drain regions scales inversely with the contact area, limiting the drive current of the transistor. Historically, planar devices relied on simple ion implantation and subsequent thermal annealing to form shallow junctions. However, these conventional junctions suffer from high sheet resistance and poor short-channel immunity at advanced dimensions.

To address these limitations, modern semiconductor manufacturing utilizes a process known as source drain recess (SDR) engineering. At its core, source drain recess is a process wherein the silicon substrate in the active areas adjacent to the gate electrode is selectively etched to create localized cavities or recesses. These recessed regions are subsequently refilled using selective epitaxial growth (SEG) of highly doped semiconductor alloys, such as silicon-germanium (SiGe) for p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) or silicon-carbon (SiC) and phosphorus-doped silicon (Si:P) for n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs). In carbon- and phosphorus-doped silicon layers, both carbon and phosphorus compete for substitutional lattice sites, making it difficult to achieve both a high strain and a low resistivity .

This architectural shift achieves two primary engineering objectives. First, it enables the integration of strain-inducing stressors directly adjacent to the channel, boosting carrier mobility through band engineering. Second, it allows process engineers to implement raised source/drain structures, which significantly increase the contact volume and permit the formation of low-resistance self-aligned silicide contacts without risking junction consumption or excessive leakage. Understanding the physical, chemical, and structural principles of the silicon recess etch is therefore foundational to mastering advanced front-end-of-line (FEOL) integration.

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Physics & Mechanism

Lattice Strain Physics and Mobility Enhancement

The integration of a recess in the source and drain regions is primarily driven by the physics of uniaxial lattice strain. For an NMOS device, introducing carbon into the silicon lattice in the recessed regions creates localized tensile strain. Because the covalent radius of carbon is smaller than that of silicon, the selective epitaxy of a silicon-carbon (SiC) alloy in the recessed source/drain regions induces lateral tensile strain and vertical compressive strain within the silicon channel. This strain tensor is quantitatively defined relative to the reference lattice constants:

$$\varepsilon_x = \frac{a_x - a_{x,\text{ref}}}{a_{x,\text{ref}}}, \quad \varepsilon_z = \frac{a_z - a_{z,\text{ref}}}{a_{z,\text{ref}}}$$

This strain breaks the six-fold degeneracy of the silicon conduction band, splitting the valleys into lower-energy twofold degenerate valleys and higher-energy fourfold degenerate valleys. Electrons preferentially populate the lower-energy valleys, which exhibit a lower transverse effective mass in the transport direction, thereby suppressing intervalley phonon scattering and enhancing electron surface mobility.

The linear-region drain-source current ($I_{ds}$) in a MOSFET highlights how surface mobility directly translates to drive capability:

$$I_{ds} = \frac{W}{L} Q_{\text{inv}} \mu_{ns} V_{ds}$$

Here, $Q_{\text{inv}}$ represents the inversion-layer sheet charge density, while $W$ and $L$ represent the channel width and length, respectively. Under strong perpendicular electric fields, carrier transport is limited by surface scattering, which is modeled using the average perpendicular field ($E_{\text{avg}}$) in the inversion layer:

$$E_{\text{avg}} = \frac{E_b + E_t}{2}$$

where $E_b$ and $E_t$ are the perpendicular fields at the bottom and top of the inversion layer, respectively. By engineering uniaxial strain via recess stressors, engineers mitigate this surface scattering, boosting the effective drive current of advanced short-channel devices.

Chemical Reaction Principles of Recess Etching

The creation of the recess cavity is accomplished via selective reactive ion etching (RIE) or dry chemical etching, often combined with wet chemical treatments to manage surface damage. Silicon recess etch chemistries typically leverage halogen-based plasmas (such as fluorine, chlorine, or bromine). Etch selectivity is the ratio of the etch rates of the different materials in an etch process [T1]. The chemical mechanism relies on the adsorption of reactive halogen radicals onto the silicon surface, followed by ion-bombardment-induced desorption of volatile silicon tetrahalides (e.g., $\text{SiF}_4$, $\text{SiCl}_4$).

During the over-etch phase of polysilicon gate patterning, an unintended silicon recess can occur due to plasma oxidation. In the presence of oxygen-containing plasmas (e.g., $\text{HBr}/\text{O}_2$), reactive oxygen species penetrate the thin gate dielectric under ion bombardment, reacting with the underlying silicon substrate to form a thin plasma-grown oxide layer. This oxidation process follows ion-assisted kinetic mechanisms rather than pure thermal diffusion. Subsequent wet cleaning steps using dilute hydrofluoric acid remove this plasma-grown oxide, leaving behind a recess in the active silicon area adjacent to the gate.

Alternative Carrier Modulation and Gate Recess Physics

While source drain recess is primarily a CMOS-centric process, analogous recess techniques are employed in high-frequency compound semiconductor devices, such as high electron mobility transistors (HEMTs). In these devices, a gate recess etch is used to define the gate foot and control the threshold voltage by thinning the barrier layer above the two-dimensional electron gas (2DEG) channel.

The process uses a dielectric (e.g., $\text{SiN}_x$) as a hard mask to define the gate morphology, reducing parasitic capacitances and enhancing the cutoff frequency. Gate recessing combines selective dry etching and wet chemical polishing to eliminate plasma-induced surface damage and achieve channel current uniformity.

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Process Principles

Designing a robust source drain recess process requires precise balancing of several chemical and physical parameters. These parameters interact directionally to govern the geometry, uniformity, and defect density of the resulting recess cavity.

[RF Bias Power] ──> Increases Ion Energy ──> Enhances Anisotropy ──> Deepens Recess Bottom
[Gas Chemistry (F/Cl/Br)] ─────────────────> Modulates Isotropics ─> Controls Lateral Undercut
[Wet Etch (TMAH/NH4OH)] ───────────────────> Crystallographic ─────> Forms Sigma-Shape (111)

Dry Etch Parameter Interactions

• Ion Energy and RF Bias Power: Increasing the radio frequency (RF) bias power shifts the etch regime toward physical sputtering, enhancing directional vertical etching. Higher bias power increases the vertical recess depth but can lead to lattice damage at the bottom of the cavity, which must be addressed prior to selective epitaxy.
• Radical-to-Ion Flux Ratio: Modulating the source power relative to the bias power changes the ratio of neutral chemical radicals to active bombarding ions. A higher chemical radical flux promotes isotropic etching, leading to lateral undercutting of the gate spacer. Conversely, halogen mixtures containing bromine promote sidewall passivation, yielding vertical, anisotropic profiles.

Profile Engineering (U-Shape vs. Sigma-Shape)

• Anisotropic Dry Etch (U-Shape): Standard RIE processes produce a U-shaped recess cavity with rounded corners. This profile is optimized by adjusting polymerizing gas additions to deposit protective liners on the spacer sidewalls, preventing lateral erosion while allowing the bottom of the trench to be etched vertically.
• Crystallographic Wet Etch (Sigma-Shape): For advanced PMOS devices, process engineers transition from a dry etch to an alkaline wet etch (using solutions such as tetramethylammonium hydroxide (TMAH) or ammonium hydroxide) after the initial dry recess. These chemistries exhibit extreme selectivity toward specific silicon crystallographic planes, etching the {100} and {110} planes at significantly higher rates than the {111} planes. This anisotropic selectivity naturally terminates the etch at the slow-etching {111} planes, creating a precise Sigma-shape (\Sigma-shape) cavity. The tip of the Sigma profile extends laterally beneath the gate spacer, positioning the subsequent SiGe stressor closer to the channel to maximize strain transfer efficiency.

Multi-Step Etch Strategies

To achieve both structural precision and low defect density, advanced nodes implement multi-stage etching schemes. An initial anisotropic dry etch defines the macro-depth of the cavity, followed by a highly selective, low-energy dry or wet "trim" etch. This secondary step removes the surface layer damaged by high-energy ion bombardment, ensuring a clean, crystalline interface for the subsequent epitaxial growth.

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Challenges & Failure Modes

The execution of a sub-nanometer source drain recess is highly sensitive to process variations. Small deviations in etch kinetics or passivation layers can lead to catastrophic electrical failures.

Profile Control and Cavity Corner Rounding

During the fabrication of gate-all-around (GAA) nanosheet transistors, a horizontal recess of sacrificial silicon-germanium layers is required to form cavities for the inner spacers. A common failure mode is corner rounding of these cavities due to diffusion-limited transport of etchants in high aspect ratio spaces.

If the cavity profile is not highly orthogonal, the subsequent deposition of the inner spacer dielectric will be non-uniform. Thin regions near the rounded corners can suffer from local dielectric breakthrough during the subsequent replacement dummy gate etch. This results in direct shorting between the metal gate stack and the epitaxial source/drain regions.

To prevent this, multi-stage etching processes are implemented where a primary lateral recess is followed by an inner trim etch to square off the cavity corners.

Rounded Cavity (Risk of spacer thinning & gate-S/D shorting):
   [Gate] 
   [Spacer]   ( ) <── Rounded cavity profile
   [Channel]

Orthogonal Cavity (Uniform spacer deposition & robust isolation):
   [Gate]
   [Spacer]   [ ] <── Squared-off profile via trim etch
   [Channel]

Active Silicon Area Recess and Plasma-Induced Damage

During the main polysilicon gate over-etch step, plasma-induced oxidation of the silicon substrate can occur. Reactive oxygen ions cross the thin gate dielectric, forming an oxide phase that consumes the active silicon. When these oxides are removed in subsequent wet cleaning steps, a recess is formed in the source/drain extensions. This unintended loss of conductive cross-section can increase parasitic series resistance and reduce transistor drive current.

Furthermore, high-energy ion bombardment during dry etching creates a damaged amorphized silicon layer at the bottom of the recess, which can lead to high junction leakage and localized dislocation defects during epitaxial growth.

Crystal Surface Preparation and Doping

The recessed silicon is prepared as a clean crystalline template for selective epitaxial growth. An oxide screen remaining on that growth surface would obstruct the intended epitaxy. Doping can instead be incorporated during epitaxial growth or introduced into the grown material in an appropriate subsequent integration sequence. Implantation damage, where implantation is used, must be considered together with activation and defect recovery; it is not a reason to describe an oxide-covered cavity as ready for epitaxy.

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Technology Node Evolution

The physical configuration and role of the source drain recess have evolved fundamentally across major technology nodes to meet scaling demands.

Planar (28nm)       FinFET (14nm/7nm)        GAA Nanosheet (Beyond 2nm)
   [Gate]               ___[Gate]___                === [Channel] ===
  ───┴───               │  ┌───┐   │                ─┬─ [Spacer]  ─┬─
 ░░░░░░░░░             ░░░ │   │ ░░░               [S/D]         [S/D]
  (Flat S/D)            (Fin Recess)             (Dielectric Isolation)

28nm Planar Node

At the 28nm Planar Flow, the source drain recess was primarily introduced to integrate embedded SiGe (eSiGe) stressors for PMOS transistors. The recess was a shallow cavity formed using a self-aligned approach relative to the gate spacer.

The primary challenge was managing the lateral undercut to prevent the growing SiGe from getting too close to the channel, which would cause short-circuit leakage, while keeping it close enough to maximize compressive stress. For an embedded SiGe stressor, in-situ doping during epitaxial growth can provide the required dopants while avoiding an unnecessary damaging implant into the stressor. Subsequent thermal integration must preserve the intended strain and junction properties.

14nm to 7nm FinFET Nodes

As the industry transitioned to 3D architectures, such as the 14nm FinFET and 7nm FinFET nodes, recess engineering became three-dimensional. Instead of etching a flat substrate, process engineers had to etch three-dimensional silicon fins (fin recess).

The fin recess etch removes the upper portion of individual silicon fins while preserving surrounding isolation and gate-sidewall protection. The STI oxide separates the etched cavities; etching the fins does not itself merge cavities across that oxide. Subsequent selective epitaxial growth can extend laterally and merge material grown from neighboring fins, depending on the intended device geometry. This distinction matters when interpreting the 7nm FinFET integration: recess formation prepares the growth surfaces, while the later epitaxial process determines whether the raised source/drain material joins across fins.

GAA Nanosheets and Beyond (Sub-2nm Nodes)

In gate-all-around nanosheet architectures, the traditional fin is replaced by a vertical stack of alternating sacrificial SiGe layers and silicon channel nanosheets. The source drain recess process in GAA involves two distinct steps:

1. Vertical Nanosheet Stack Etch: A highly directional anisotropic dry etch that cuts through the entire Si/SiGe stack to define the vertical boundaries of the source/drain regions.
2. Lateral Sacrificial Layer Recess: A highly isotropic dry chemical etch that selectively recesses the sacrificial SiGe layers horizontally relative to the silicon channel layers, creating cavities for the inner spacers.

At these advanced geometries, the source/drain design must account for the intended electrical connection. In advanced backside power delivery schemes, the source/drain epitaxial structure can feature a lower portion that extends vertically below a bottom surface of the vertical metal gate structure and into the backside ILD layer . This geometry can allow electrical coupling to a backside contact that supplies power to the source/drain; the geometry alone does not establish suppression of sub-fin leakage.

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Related Processes

The source drain recess does not exist in isolation; it is a critical link in a tightly integrated sequence of front-end processes.

[S/D Recess Etch] ──> [Pre-Epi Wet Clean] ──> [Selective Epitaxy (SEG)] ──> [Salicide Contact]

Selective Epitaxial Growth (SEG)

The recess cavity is designed specifically to host the subsequent selective epitaxial growth of SiGe, SiC, or highly doped Si. The shape, depth, and surface cleanliness of the recess directly determine the crystal quality of the epitaxial layer.

Any residual amorphized silicon, dry etch polymer, or native oxide at the bottom of the recess will cause crystallographic defects, such as threading dislocations or stacking faults, which degrade carrier mobility and increase junction leakage.

Advanced Wet Cleaning

Immediately following the recess etch and prior to epitaxial growth, wafers undergo critical wet cleaning steps. These cleans typically utilize dilute hydrofluoric acid to remove native oxides and restore a hydrogen-terminated silicon surface, preventing oxidation before the wafer enters the epitaxy chamber.

In some cases, specialized organic or polymer strip chemistries are used to remove halogenated carbon residues left behind by the RIE process without etching the sensitive gate spacer dielectrics.

Self-Aligned Silicide (Salicide) Contact Formation

Following selective epitaxy, the source and drain regions are metallized to form low-resistance contacts. This process, known as self-aligned silicide or salicide, involves depositing a transition metal (such as nickel or cobalt) and performing a thermal anneal to react the metal with the underlying silicon or silicon alloy.

The depth and profile of the original source drain recess must be optimized to ensure that the silicide reaction does not consume too much of the shallow junction, which would lead to junction penetration and high contact-to-substrate leakage. The introduction of nickel silicide technology has been crucial in maintaining thin, highly conductive contact layers on recessed and raised source/drain architectures.

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Future Outlook

As scaling approaches atomic dimensions, source drain recess technology is evolving toward atomic-level precision and complex 3D integration.

Atomic Layer Etching (ALE)

To overcome the physical limitations of conventional reactive ion etching—such as aspect ratio dependent etching (ARDE) and plasma damage—the industry is transitioning toward atomic layer etching (ALE). ALE decouples the etch process into sequential, self-limiting surface modification and desorption steps.

By utilizing ALE for the silicon recess, process engineers can achieve sub-nanometer depth control with minimal plasma-induced damage, ensuring pristine crystalline surfaces for subsequent epitaxy.

Complementary FET (CFET) Integration

The next major architectural transition beyond GAA nanosheets is the complementary field-effect transistor (CFET), where n-type and p-type nanosheet transistors are stacked directly on top of each other.

This extremely dense 3D integration presents unprecedented challenges for the source drain recess process, requiring high aspect ratio etches that can selectively recess different materials at different vertical levels of the stack. Process engineers must develop multi-level recess and isolation schemes to allow separate, vertically stacked n-type and p-type selective epitaxy processes within the same active cell.

Alternative High-Mobility Channel Materials

The potential transition from silicon channels to alternative high-mobility materials, such as germanium (Ge) or III-V compound semiconductors (e.g., InGaAs), requires new recess chemistry development.

Because these materials possess lower surface bonding energies than silicon, they are sensitive to thermal and plasma-induced degradation. The recess processes for these materials must operate at lower thermal budgets and utilize highly selective chemical dry etches to prevent stoichiometry modification and defect generation.

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