Introduction
As complementary metal-oxide-semiconductor (CMOS) technology scaled down into the submicron regime, maintaining device reliability while boosting performance became a monumental challenge for semiconductor manufacturers . Historically, operating voltages did not scale down in direct proportion to the physical gate length, leading to extremely high lateral electric fields within the transistor channel . To mitigate the severe degradation caused by these high electric fields, process engineers introduced the lightly doped drain (LDD) structure , .
In a p-type metal-oxide-semiconductor (PMOS) transistor, this structural modification is known as the p-type lightly doped drain (PLDD) or P-type LDD . The PLDD is a shallow, moderately doped region positioned between the highly doped source/drain (S/D) contacts and the channel , . By inserting this transition region, the abruptness of the junction is reduced, allowing the drain voltage to drop across a wider depletion region, which effectively lowers the peak lateral electric field .
In modern manufacturing, such as in the 28nm Planar Flow, PLDD engineering is a critical factor in optimizing transconductance ($G_m$), reducing subthreshold leakage current ($I_{off}$), and suppressing short-channel effects (SCE) , . Understanding the physical mechanisms, process dependencies, and failure modes of the PLDD is essential for any process integration or device engineer working on advanced logic technologies .
Physics & Mechanism
The operational physics of the PLDD relies on the fundamental relationship between doping profiles, space charge regions, and electrostatic fields . According to Poisson’s equation, the spatial gradient of the electric field ($E$) is directly proportional to the net charge density ($\rho$) in the depletion region :
$$\nabla \cdot \mathbf{E} = \frac{\rho}{\varepsilon_{si}}$$
Where $\varepsilon_{si}$ represents the permittivity of silicon . In an abrupt, non-LDD junction, a heavy p-type ($P^+$) doping abruptly meets the n-type well, concentrating the space charge in a very narrow depletion layer . Under high drain bias, this narrow depletion layer yields an extremely sharp potential drop, generating an intense peak lateral electric field near the drain edge , .
By introducing a graded $P^+ / P^- / N$ doping profile via the PLDD, the space charge is distributed over a physically wider depletion width . This spatial broadening of the depletion region drops the same drain-to-source voltage over a larger distance, thereby dramatically decreasing the peak value of the lateral electric field .
Carrier Transport and Reliability Engineering
Mitigating the peak lateral electric field directly addresses several key high-field reliability issues:
- Impact Ionization and Avalanche Breakdown: High-energy carriers (hot carriers) accelerated by the lateral electric field can collide with the silicon lattice, breaking covalent bonds and generating secondary electron-hole pairs . This impact ionization can trigger avalanche breakdown or induce parasitic bipolar turn-on (Engineering Practice). Lowering the peak field via the PLDD suppresses the exponential generation of these hot carriers .
- Hot-Carrier Injection (HCI): Hot carriers with energies surmounting the energy barrier between the silicon conduction/valence bands and the gate dielectric conduction/valence bands can inject themselves into the gate oxide or spacer dielectric . Once trapped, these carriers alter the local electrostatic potential, causing threshold voltage ($V_t$) shift and transconductance ($G_m$) degradation , .
PMOS vs. NMOS LDD Physics
While both n-channel and p-channel devices utilize LDD structures, PMOS transistors exhibit unique physical characteristics due to the nature of hole transport , . Holes have a significantly lower impact ionization coefficient and lower mobility in silicon compared to electrons , . This initially made PMOS devices less susceptible to classical hot-electron degradation than their n-type lightly doped drain (NLDD) counterparts .
However, because holes have a lower injection barrier at the silicon/gate-oxide interface than electrons, hot-hole injection remains a severe reliability concern in submicron PMOS devices , . Furthermore, the higher diffusion rate of boron (the primary p-type dopant) relative to arsenic or phosphorus requires tighter thermal budget control to prevent the PLDD from diffusing too deep into the channel , .
Process Principles & Integration
The integration of the PLDD into a standard CMOS process flow requires precise sequence coordination to protect the channel and define the shallow junction extensions , .
Gate Patterning & Etch (Conventional/Dummy Gate)
│
▼
PLDD / Extension Ion Implantation
(Self-aligned to the Gate Edge)
│
▼
Spacer Deposition and Etch
(Oxide/Nitride Conformal Layers)
│
▼
Heavily Doped S/D Ion Implantation
(Offset from Channel by Spacer Width)
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Rapid Thermal Annealing (RTA)
(Dopant Activation & Damage Repair)
Step-by-Step Integration Flow
1 . Gate Patterning: The process begins after gate stack deposition and lithographic definition, where a conventional poly-silicon gate or a sacrificial dummy gate is etched . 2. PLDD Implantation: Ion implantation is performed using the gate electrode as a self-aligned mask , . This ensures that the PLDD region aligns perfectly with the gate edge . Photolithography masks are used to protect the NMOS regions while exposing the PMOS regions for the p-type dopant species , . 3. Spacer Formation: A conformal dielectric layer (typically silicon dioxide, silicon nitride, or a bilayer of both) is deposited and anisotropically dry-etched to form gate sidewall spacers , . 4. Heavily Doped Source/Drain Implantation: A high-dose, low-energy $P^+$ ion implantation is performed . The sidewall spacers act as a physical offset mask, keeping the highly concentrated $P^+$ dopants away from the gate edge, preserving the lightly doped $P^-$ extension under the spacer , . 5. Activation Anneal: A rapid thermal annealing (RTA) step is executed to activate the implanted dopants and repair crystal lattice damage caused by the ion bombardment , (Engineering Practice).
Directional Parameter Relationships
The performance and electrostatic integrity of the PMOS device are highly sensitive to the PLDD process parameters:
- Implant Energy vs . Junction Depth ($X_j$): Increasing the PLDD implant energy drives the dopants deeper into the silicon substrate . A deeper junction increases charge sharing between the drain and the channel, which worsens SCE, increases drain-induced barrier lowering (DIBL), and accelerates $V_t$ roll-off , . Therefore, reducing implant energy is crucial for maintaining shallow junctions .
- Implant Dose vs. Series Resistance ($R_{sd}$): Increasing the PLDD dopant dose lowers the parasitic series resistance of the extension region . However, a higher dose increases the carrier concentration gradient at the channel junction, raising the peak lateral electric field and accelerating HCI degradation , . Process engineers must balance this trade-off to optimize both device speed and lifetime .
- Tilt Angle and Halo Co-implants: To further suppress DIBL, the PLDD implant is often accompanied by an angled, opposite-type "halo" or "pocket" implant (e (Engineering Practice).g., n-type arsenic or phosphorus for PMOS) (Engineering Practice). Increasing the tilt angle of the halo implant places dopants deeper under the gate, raising the local channel doping at the drain edge and preventing punch-through leakage .
- Annealing Thermal Budget vs (Engineering Practice). Profile Abruptness: High-temperature activation is needed to achieve low sheet resistance, but excessive thermal budgets cause lateral diffusion of boron , (Engineering Practice). This lateral diffusion reduces the effective channel length ($L_{eff}$) and increases gate-to-drain overlap capacitance ($C_{gd}$), which degrades high-frequency performance .
Challenges & Failure Modes
As device geometries shrink, the PLDD region becomes a focal point for physical and electrical failure modes (Engineering Practice).
1. Carrier Freeze-out at Cryogenic Temperatures
In low-temperature or deep-cryogenic applications (such as space electronics or quantum computing interfaces), PMOS devices experience carrier freeze-out . Because the ionization of boron dopants in the lightly doped $P^-$ region is thermally activated, reducing the temperature restricts the available thermal energy required to transition electrons from the valence band to the acceptor energy levels , . This causes a drastic reduction in free hole concentration, leading to an exponential increase in the PLDD series resistance ($R_{sd}$), severe transconductance degradation, and restricted linear-region drive current .
2. Spacer Charge Trapping and Total Ionizing Dose Degradation
In environments exposed to ionizing radiation (e .g., aerospace applications), the dielectric spacer overlying the PLDD region acts as a charge trap . Total ionizing dose (TID) radiation generates electron-hole pairs within the spacer oxide and nitride layers . While electrons quickly drift out due to their higher mobility, positive holes become trapped near the Si/dielectric interface .
In PMOS devices, this accumulation of positive charge above the $P^-$ extension acts to deplete the underlying p-type carriers . The resulting depletion of holes increases the local series resistance ($R_{sd}$), degrading the transistor's drive current . Concurrently, ionizing radiation liberates hydrogen ions ($H^+$) from the spacer layers, which migrate to the gate oxide interface and de-passivate Si-H bonds, generating interface states that shift the threshold voltage . This migration process is thermally activated and follows an Arrhenius behavior:
$$D = D_0 e^{-\frac{E_a}{kT}}$$
Where $D$ is the diffusion coefficient, $E_a$ is the activation energy, and $k$ is the Boltzmann constant .
3. Boron Penetration
Since boron is a relatively small atom, it exhibits a high diffusion rate in silicon and silicon dioxide (Engineering Practice). During high-temperature activation steps, boron implanted in the PLDD region or the gate can easily diffuse through thin gate oxides into the underlying channel region . This boron penetration alters the channel doping concentration, leading to uncontrolled threshold voltage shifts, increased subthreshold swing ($S$), and severe device-to-device non-uniformity .
Technology Node Evolution
The design of the PMOS drain extension has undergone radical structural transformations as the industry transitioned from planar to three-dimensional architectures .
Planar Nodes (e *(Engineering Practice)*.g., 28nm) FinFET Nodes (e *(Engineering Practice)*.g., 14nm / 7nm)
┌───────────────────────────────┐ ┌───────────────────────────────┐
│ • Ion-implanted PLDD │ │ • Conformal S/D Extensions │
│ • Traditional oxide/nitride │ ───> │ • In-situ boron-doped SiGe │
│ spacers │ │ • Epitaxial strain generation │
│ • Subthreshold roll-off limit │ │ • Complex 3D fin gating │
└───────────────────────────────┘ └───────────────────────────────┘
Planar Nodes (e [T3].g., 28nm)
In the planar era, exemplified by the 28nm Planar Flow, the PLDD was primarily defined by standard ion implantation combined with halo implants to prevent subthreshold punch-through , . The focus was on optimizing spacer thickness and optimizing the rapid thermal anneal to balance the tradeoff between overlap capacitance and series resistance , (Engineering Practice).
FinFET Era (e.g., 14nm to 7nm)
With the introduction of the 14nm FinFET and 7nm FinFET architectures, the physical channel became a thin silicon fin wrapped on three sides by the gate electrode , (Engineering Practice). This multi-gate geometry provided superior electrostatic control, reducing the absolute necessity for deep LDD profiles to suppress DIBL .
However, the narrow fin geometries introduced a major challenge: extremely high parasitic resistance in the source and drain regions (Engineering Practice). To resolve this, standard ion-implanted PLDDs were largely replaced by selective epitaxial growth (SEG) of silicon-germanium (SiGe) in the source/drain cavities (Engineering Practice). The SiGe is in-situ doped with boron to form highly conductive, ultra-shallow, and conformal S/D extensions . Furthermore, the larger lattice constant of Germanium relative to Silicon induces compressive stress along the PMOS channel, which significantly boosts hole mobility , (Engineering Practice).
Gate-All-Around and Nanowire Architectures
In gate-all-around (GAA) nanosheets and vertical nanowire structures, traditional line-of-sight ion implantation for PLDD becomes physically impossible due to shadowing effects and extreme vertical geometries , . Modern GAA nodes utilize atomic layer doping or conformal epitaxial extension growth combined with inner spacers to define the exact boundary between the channel and the heavily doped reservoir, ensuring precise channel length control down to the sub-10nm scale , (Engineering Practice).
Related Processes
The PLDD does not exist in isolation; its design and thermal budget are intimately linked to several key adjacent process modules:
- Spacer Dielectric Deposition and Etch: The physical dimensions and material quality of the spacer directly define the offset of the heavy S/D implant . Standard spacers utilize low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) to ensure conformal coverage over the gate step before anisotropic dry etching , .
- Silicide Engineering: To establish low-resistance contacts, a self-aligned silicide (salicide) process is executed . The gate spacer prevents the silicide metals (such as cobalt or nickel) from bridging the gate and the S/D regions, which would cause catastrophic electrical shorts , (Engineering Practice). In advanced nodes, nickel silicide is widely used due to its low resistivity and reduced silicon consumption, but its thermal budget is highly constrained, requiring low-temperature processing after the high-temperature PLDD activation , (Engineering Practice).
- Salicide Blocking: In specific analog or high-voltage layout regions where high resistance is intentionally required, a salicide block dielectric layer is deposited to prevent metal-silicon reaction, preserving the high sheet resistance of the underlying lightly doped LDD region .
- Gate-Last HKMG Integration: In a high-k metal gate (HKMG) gate-last or replacement metal gate (RMG) flow, the sacrificial dummy gate is removed and replaced with the high-k dielectric and work-function metals after the high-temperature S/D and PLDD activation anneals , (Engineering Practice). This "gate-last" sequence prevents the delicate metal gates and high-k stacks from experiencing severe thermal degradation during dopant activation , (Engineering Practice).
Future Outlook
As the semiconductor industry marches toward complementary FET (CFET) architectures—where nanosheet PMOS and NMOS devices are vertically stacked on top of each other—PLDD and junction extension engineering face unprecedented integration hurdles . In a CFET, the bottom and top channel regions must be doped independently (Engineering Practice).
Since traditional line-of-sight ion implantation cannot selectively target the bottom channel without doping the top channel, the industry is transitioning toward advanced chemical processing . This includes the use of highly selective isotropic atomic layer etching (ALE) to carve out precise inner-spacer cavities, followed by selective, conformally grown in-situ doped epitaxial layers (Engineering Practice). Controlling the thermal budget of the top device to prevent the out-diffusion of the bottom device's PLDD profile remains one of the most active areas of research in sub-2nm node pathfinding .