Introduction
In modern very large scale integration (VLSI) devices, establishing high-quality electrical contacts between active semiconductor regions and the metal routing network is a primary performance bottleneck. As transistor dimensions shrink to nanometer scales, the parasitic series resistance at the source/drain (S/D) regions increases drastically, degrading drive currents and operating speeds. To address this challenge, transition metal silicides are widely integrated as low-resistance contact materials at the active interface. These silicides are formed directly through a solid-state reaction between a deposited metal and the silicon substrate, providing a metallic contact layer that minimizes contact resistance.
Historically, titanium silicide and cobalt silicide were the primary materials of choice for self-aligned silicide (salicide) applications. However, as technology nodes scaled, these materials encountered severe limitations: titanium silicide suffered from high sensitivity to narrow-linewidth scaling due to a nucleation-controlled phase transition, while cobalt silicide consumed excessive silicon, threatening the integrity of ultra-shallow S/D junctions.
To overcome these scaling limits, nickel monosilicide (NiSi) emerged as a dominant contact material. NiSi exhibits low electrical resistivity while offering several distinct advantages: it forms at lower thermal budgets, consumes significantly less silicon during the reaction, and maintains low resistance even on narrow silicon lines. By contacting the entire source and drain active areas rather than restricting silicide strictly to narrow contact holes, the total contact resistance is reduced by expanding the effective contact interface area . Unlike standard unpatterned metal depositions, silicide layers can be formed in a self-aligned manner relative to the gate structure, minimizing the parasitic sheet resistance between the contact and the active channel . By integrating NiSi through a self-aligned silicide process flow, semiconductor manufacturers successfully minimized contact resistance across deep-submicron device generations.
Process map
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Physics & Mechanism
The formation of nickel silicides on a silicon substrate is a thermally driven solid-state reaction governed by thermodynamics, chemical potential gradients, and diffusion kinetics. Under typical processing conditions, the nickel-silicon system sequentially transitions through several stoichiometric phases before reaching the final stable phase.
Pre-Silicidation Interface Alloying
An essential starting point of the reaction occurs before thermal treatment is applied. During the physical vapor deposition (PVD) of nickel onto a silicon substrate at room temperature, a non-equilibrium interfacial alloy layer forms spontaneously. This initial layer, typically identified as a nickel-rich phase such as Ni₃Si, is favored by the high chemical affinity of nickel for silicon and a low insertion energy barrier. First-principles density functional theory calculations demonstrate that nickel atoms possess a driving force to penetrate the silicon surface layers and occupy subsurface interstitial sites, inducing local bond rearrangement and atomic mixing. This disordered, nickel-rich interfacial layer serves as a seed template that guides phase evolution during subsequent thermal processing.
[ As-Deposited Room-Temp State ]
+-----------------------+
| Nickel Metal (Ni) |
+-----------------------+
| Interfacial Ni3Si | <-- Spontaneous room-temperature alloying
+-----------------------+
| Silicon Substrate |
+-----------------------+
Thermal Phase Transformations and Diffusion Kinetics
When the temperature is elevated during thermal processing, the system undergoes a series of sequential phase transformations. The core phase evolution follows the pathway:
Ni₂Si → NiSi → NiSi₂
At lower temperatures, the reaction is dominated by the diffusion of metal atoms. Nickel acts as the primary diffusing species, rapidly migrating into the silicon lattice. The initial crystalline phase to emerge is the orthorhombic, nickel-rich phase (Ni₂Si), accompanied by a reciprocal diffusion of silicon into the metal overlayer.
As the temperature is elevated further, the system transitions into the monosilicide phase, NiSi, which is the technologically desired low-resistance phase. This conversion is driven by vacancy-assisted atomic migration. Mechanistically, the NiSi crystal structure can be described as an expanded and distorted silicon lattice in which nickel atoms occupy distorted octahedral interstitial channels. Because the silicon atomic framework is largely preserved, the volume change and silicon consumption associated with NiSi formation are remarkably low compared to alternative silicides.
Si lattice (distorted) + Ni (interstitial) → Orthorhombic NiSi
At excessively high temperatures, the monosilicide phase undergoes a nucleation-controlled transformation to the silicon-rich disilicide phase (NiSi₂). Unlike the diffusion-controlled formation of earlier phases, the nucleation of NiSi₂ is hindered by a high kinetic barrier. When this barrier is overcome, the high-resistivity NiSi₂ phase grows epitaxially on the silicon substrate, which dramatically increases sheet resistance and consumes twice as much silicon substrate, risking the disruption of shallow active junctions.
Role of Platinum Alloying
To suppress the undesirable NiSi₂ phase transition, platinum is commonly added to the nickel metal target during deposition. Platinum forms solid solutions within the nickel silicide lattice and alters the system's thermodynamics and kinetics.
- Thermodynamic Stabilization: Platinum exhibits high solubility in the monosilicide phase but low solubility in the disilicide phase. By preferentially occupying metal sites in the NiSi lattice, platinum lowers the free energy of the monosilicide phase, making the nucleation of NiSi₂ thermodynamically unfavorable.
- Kinetic Diffusion Barrier: Because platinum atoms diffuse at a slower rate than nickel, they tend to segregate at the silicide/silicon interface. This segregated layer acts as a physical diffusion barrier, reducing the flux of diffusing species and widening the thermal processing window for NiSi stability.
Process Principles
The structural, mechanical, and electrical properties of the resulting NiSi film are highly sensitive to process parameters, requiring careful optimization of processing conditions.
Temperature and Thermal Budget Control
The phase composition and film morphology are directly controlled by the thermal budget, which is a function of annealing temperature and duration. Rapid thermal annealing (RTA) is typically employed to control the solid-state reaction with high precision. Lower thermal budgets ensure that the reaction halts at the low-resistance NiSi phase, preventing the high-temperature transition to the high-resistivity NiSi₂ phase. However, if the thermal budget is insufficient, unreacted nickel-rich phases may persist, resulting in higher sheet resistance and non-uniform electrical contacts.
Substrate Strain Modulation
Mechanical stress within the substrate significantly influences the thermal stability of the NiSi film. High-temperature processing of thin films generates compressive stress within the silicide due to the mismatch in thermal expansion coefficients between the metal silicide and the underlying silicon. This accumulated stress drives morphologic degradation, causing the continuous thin film to break apart into isolated clusters or islands, a phenomenon known as agglomeration.
By utilizing biaxially tensile-strained silicon substrates (such as those grown epitaxially on silicon-germanium buffers), the effective compressive stress in the NiSi film is significantly reduced during heating. The larger in-plane lattice constant of the strained silicon substrate minimizes the interface energy and reduces the driving force for thin-film morphological breakdown. Consequently, tensile-strained substrates shift the onset of agglomeration to higher temperatures, enhancing the thermal stability of the contact structure.
Doping and Impurity Effects
The electrical behavior of the silicide contact is highly dependent on the dopant profiles in the underlying silicon. High dopant concentrations (using donor or acceptor impurities) modulate the band bending at the metal-semiconductor interface, reducing the width of the Schottky barrier. This enables efficient carrier transport via quantum mechanical tunneling, which is critical for achieving low contact resistance.
However, high dopant concentrations can also interact with the silicidation kinetics. Heavily doped substrates can alter the diffusion coefficients of nickel and silicon atoms, sometimes retarding the silicidation rate or shifting the optimal phase-formation temperature window. Additionally, the formation of the silicide can cause dopant segregation or "snowplowing" at the advancing silicide front, where dopant atoms are pushed ahead of the reaction interface, creating a highly doped region immediately beneath the contact.
Challenges & Failure Modes
Despite its excellent contact properties, integrating nickel silicide into advanced semiconductor technologies presents major engineering challenges. Several physical and chemical failure modes must be mitigated during manufacturing.
[ Typical Failure Modes in NiSi Contact Layers ]
1 . Agglomeration (Islanding) 2 . Phase Transition (NiSi2)
+---+ +---+ +---+ +-------------------------+
|NiS| |NiS| |NiS| (Discontinuous) | NiSi2 (Cubic) | (High Rs)
===+===+===+===+===+===+=== ===+========================+===
| Silicon Substrate | | Silicon Substrate |
3 . Lateral Encroachment 4 . Interface Contamination
+-------+ (Gate) +-------------------------+
|Spacer | | Nickel Overlayer |
+--+-------+--+ +-------------------------+
| | Ni | | <-- Inwards leak |~ ~ Native Oxide Barrier ~| (Discontinuous)
==+==+=======+==+=== ==+=========================+===
| S/D Channel | Silicon Substrate |
Thin-Film Agglomeration (Islanding)
Agglomeration is a primary morphologic failure mode of NiSi films exposed to high temperatures. At elevated temperatures, the thin, continuous silicide film attempts to minimize its total surface and interface energies by breaking up into isolated, sphere-like islands. This process is highly dependent on the initial thickness of the film and the grain structure of the silicide. Thinner silicide films possess a higher surface-to-volume ratio and are more susceptible to this thermal instability. Agglomeration destroys the electrical continuity of the contact layer, leading to a dramatic increase in sheet resistance and, in severe cases, open-circuit failures.
Phase Degradation to NiSi₂
The transition from the low-resistance NiSi phase to the high-resistance, cubic NiSi₂ phase is a major thermal stability concern. The NiSi₂ phase requires deep silicon consumption, which can penetrate through shallow S/D junctions, leading to junction leakage and potential source-to-drain short circuits. This phase transition is nucleation-controlled and occurs rapidly once the thermal threshold is crossed. Controlling the thermal budget and incorporating platinum are the primary methods used to prevent this degradation mode.
Lateral Encroachment and Junction Spiking
Nickel atoms are mobile interstitial diffusers in silicon. During the thermal reaction, if the lateral diffusion of nickel is not strictly confined, metal atoms can migrate horizontally beneath the gate spacer oxide and encroach into the active channel region. This lateral encroachment, often called "junction spiking" or "silicide-induced defects," creates leakage paths between the source and drain, degrades gate oxide reliability, and can cause device shorting.
Native Oxide and Interface Contamination
The solid-state silicidation reaction is sensitive to the cleanliness of the starting silicon surface. The presence of even a thin native oxide (SiO₂) or chemical residue acts as a diffusion barrier, blocking the interaction between the deposited nickel and the silicon substrate. This results in an incomplete or non-uniform silicidation reaction, causing local variations in silicide thickness, discontinuous films, and elevated contact resistance.
Technology Node Evolution
The implementation of nickel silicide has evolved significantly as transistor architectures shifted from planar to three-dimensional structures.
28nm Planar Node
At the planar 28nm Planar Flow, NiSi became the industry standard contact material. The low thermal budget of NiSi was compatible with the gate-last integration schemes of this node. To prevent the agglomeration of ultra-thin films, co-deposition of a small percentage of platinum was widely adopted, ensuring stable contact resistance across both n-type and p-type S/D active regions.
14nm FinFET Node
With the introduction of the 14nm FinFET architecture, silicidation was forced to transition from planar surfaces to three-dimensional fins. This structural transition introduced several unique challenges:
- Conformality: The deposited nickel-platinum film had to coat the vertical sidewalls of high-aspect-ratio fins conformally to ensure uniform silicide thickness and avoid localized thinning.
- Crystallographic Dependency: Silicidation rates and phase transformations vary across different silicon crystal orientations. Fin structures expose multiple crystallographic planes, causing complex, non-uniform reaction fronts that required tighter process margin controls.
- Mechanical Stress: The highly non-planar geometry of FinFETs amplified mechanical stress, increasing the driving force for local silicide defect generation and requiring optimized platinum concentrations to stabilize the monosilicide phase.
7nm FinFET and Beyond
At the 7nm FinFET node and beyond, contact scaling reached extreme physical limits where the contact trench width shrunk to only a few nanometers. At these dimensions, contact resistance became heavily dominated by the quantum mechanical Schottky barrier height at the metal-semiconductor interface.
To achieve lower contact resistance, the semiconductor industry began transitioning from NiSi to alternative metallization systems, such as cobalt (Co) or ruthenium, which offer excellent fill characteristics in extremely small geometries and lower overall contact resistivity. Despite this transition for primary contacts, nickel-based silicides remain critical for specialized contact schemes and highly doped source/drain structures.
Related Processes
The successful integration of nickel silicide relies on tight coordination with several adjacent process steps in the front end of line (FEOL).
[ Pre-Clean ] --> [ PVD Deposition ] --> [ 1st RTA Anneal ]
(Native oxide removal) (Ni/Pt co-deposition) (Ni2Si phase formation)
| |
v v
[ Selective Metal Etch ] <-- [ 2nd RTA Anneal (NiSi) ] <-- [ Selective Strip ]
(Final clean/passivate) (Monosilicide conversion) (Remove unreacted Ni/Pt)
Surface Pre-Clean
Before nickel deposition, the active silicon areas must be completely cleared of native oxide and chemical contaminants. This is typically achieved using wet clean chemistries, such as dilute hydrofluoric acid or plasma-based dry cleans, which remove silicon dioxide without eroding adjacent isolation structures or gate spacers.
Thin-Film Deposition
Following the pre-clean, a thin layer of nickel, typically co-deposited with a small atomic percentage of platinum, is deposited across the wafer using high-conformality PVD. In advanced structures, chemical vapor deposition or atomic layer deposition (ALD) may be evaluated to achieve required step coverage on complex three-dimensional features.
Thermal Processing (Two-Step RTA)
The silicidation reaction is typically executed using a two-step RTA process to control phase formation and prevent lateral encroachment:
- First Anneal: A low-temperature thermal step is applied to drive the diffusion of nickel into the silicon, forming the transition metal-rich phase (Ni₂Si).
- Selective Metal Strip: A wet chemical etch is performed to selectively remove unreacted metal from dielectric surfaces (such as gate spacers and isolation regions) while leaving the reacted metal-silicide phase intact. This selective strip is critical to avoid electrical shorting between the gate and the source/drain. The non-silicided regions can be defined by a salicide block layer if specific resistors are required.
- Second Anneal: A second, higher-temperature thermal step is applied to convert the metal-rich phase into the highly conductive monosilicide NiSi phase.
Future Outlook
As the semiconductor industry advances toward gate-all-around (GAA) nanosheets, fork-sheet architectures, and 3D integrated circuits, traditional front-side contact schemes face severe physical layout constraints. This has driven intense research into back-side power delivery networks (BSPDNs), where power lines are routed from the back of the silicon wafer to free up routing resources on the front side.
[ Advanced Backside Contact Integration ]
Front-Side Contact / Interconnect
+-----------------------------+
| FEOL S/D |
+-----------------------------+
| High-Temp FEOL Silicide | <-- Formed prior to BEOL
+-----------------------------+
| Wide Placeholder Structure | <-- Protects active area during
+-----------------------------+ back-side wet etch processing
| Backside Metal Contact |
+-----------------------------+
A key enabling technology in this paradigm is the development of direct back-side contacts (DBCs). In these schemes, back-side contact structures are connected to the S/D regions from the bottom of the active device. Integrating the silicide layer for these back-side contacts during the standard back end of line (BEOL) process limits the silicidation annealing temperature to prevent the melting or degradation of low-melting-point front-side metals.
To bypass this thermal budget constraint, novel FEOL integration schemes have been developed where a high-quality silicide layer is formed at high temperatures using metal placeholder structures during the early FEOL stage. By forming the silicide first, the system achieves a stable, low-resistance, and high-quality NiSi contact.
Furthermore, to protect the active S/D regions from chemical erosion during back-side wet etching and substrate removal, engineers utilize widened placeholder structures. These widened geometries protect delicate semiconductor interfaces and expand the effective contact area, significantly reducing interface resistance and enabling the continuous scaling of high-performance logic devices.
References
Silicon VLSI Technology - Full
James D. Plummer, Michael D. Deal, Peter B. Griffin
Silicon VLSI Technology · ISBN 978-0130850379