Introduction
In modern integrated circuit manufacturing, the successful transition of electrical signals from the active silicon channels of transistors to the metal interconnect network is a fundamental requirement for device operation . This transition is mediated by contact metallization, which must exhibit exceptionally low contact resistance and high reliability [P3, T2]. Historically, the industry relied on materials such as titanium silicide ($TiSi_2$) and cobalt silicide ($CoSi_2$) to form these contacts . However, as transistor dimensions scaled down, the high-temperature processing requirements and line-width dependency of these materials became severe bottlenecks . This drove the transition to nickel silicide ($NiSi$) as the primary contact material, owing to its low resistivity, low thermal budget, and minimal line-width sensitivity .
Despite its advantages, pure nickel silicide suffers from poor thermal stability and a tendency to transition into a high-resistance disilicide ($NiSi_2$) phase or undergo morphological agglomeration at elevated temperatures [P2, P3]. To overcome these physical limitations, physical vapor deposition (PVD) processes incorporate a small atomic fraction of platinum into the nickel film, forming a nickel platinum (NiPt) alloy [P2, A1].
The utilization of NiPt is a cornerstone of self-aligned silicide (SALICIDE) technology, enabling the simultaneous formation of low-resistance Ohmic contacts on the gate, source, and drain regions without requiring complex lithographic alignment . Understanding the thermodynamic, kinetic, and physical principles of NiPt is essential for semiconductor engineers working on advanced technology nodes, where interface engineering dictates overall device performance .
Physics & Mechanism
The integration of NiPt relies on a complex solid-phase reaction (SPR) between the deposited metal alloy and the underlying silicon substrate . To understand why the addition of platinum stabilizes the silicide contact, we must examine the phase formation sequence, thermodynamic driving forces, and interface physics that govern the system [P2, P3, T2].
Solid-Phase Reaction and Phase Sequence
When a pure nickel thin film is deposited on a silicon substrate and annealed, it undergoes a sequential series of phase transformations [P2, P3]. Kinetically, the reaction begins with the diffusion of nickel atoms into the silicon lattice, forming metal-rich phases such as $Ni_2Si$ . Upon further heating, the system transitions to the low-resistance monosilicide ($NiSi$) phase, which is the target phase for optimal electrical performance . However, at higher temperatures, the system reaches the thermodynamic threshold to form the disilicide ($NiSi_2$) phase, which features a higher resistivity and consumes significantly more silicon, threatening shallow junction integrity [P2, P3].
In the ultra-thin regimes (sub-10 nm) required by modern devices, the interface-to-volume ratio increases dramatically, meaning that interfacial energy terms begin to dominate the total Gibbs free energy of the system . Under these conditions, the phase formation sequence changes abruptly . The first phase to nucleate is typically epitaxial h-$Ni_2Si$, which minimizes the interface energy mismatch with the silicon substrate . In extremely thin films, intermediate phases are often bypassed, and the system can transition directly to $NiSi_2$ at temperatures far below those observed in thick films .
Thermodynamic Stabilization via Platinum Alloying
The addition of platinum to form a NiPt alloy fundamentally alters the thermodynamic and kinetic landscape of the solid-phase reaction [P2, P3]. Because platinum is completely miscible with nickel, they form a pseudo-ternary $Ni_{1-x}Pt_xSi$ solid solution during the reaction .
According to classical nucleation theory, the formation of a new phase requires overcoming a nucleation barrier ($\Delta G^*$), which is a function of the bulk free energy change ($\Delta G_v$) and the interfacial energy ($\gamma$) (Engineering Practice):
$$\Delta G^* \propto \frac{\gamma^3}{(\Delta G_v)^2}$$
The inclusion of platinum increases the bulk stability of the monosilicide phase and increases the structural mismatch and interfacial energy associated with nucleating the cubic $NiSi_2$ phase [P2, P3]. Consequently, the nucleation temperature of the undesirable high-resistance disilicide phase is shifted to much higher temperatures [P2, P3]. Furthermore, the alloy suppresses the phenomenon of "texture inheritance," wherein the crystallographic orientation and grain boundaries of the initial metal-rich phases dictate the morphology of the final silicide, thereby mitigating grain boundary grooving and physical film agglomeration [P2, P3].
[Deposited NiPt Alloy on Si]
│
▼ (RTA-1: Low Temperature)
[Epitaxial h-Ni2Si Phase + Unreacted NiPt] <-- Pt stabilizes interface energy [P2]
│
▼ (Selective Wet Etch & RTA-2: Higher Temperature)
[Stable Low-Resistance Ni(Pt)Si Monosilicide] <-- Pt suppresses NiSi2 transition [P2, P3]
Ohmic Contact Physics and Work Function Tuning
From a device physics perspective, the primary objective of the NiPt silicide contact is to establish a low-resistance Ohmic contact by minimizing the Schottky barrier height ($\Phi_B$) at the metal-semiconductor interface [P3, T2]. The contact resistance ($R_c$) scales exponentially with the barrier height and is inversely proportional to the square root of the active dopant concentration ($N_D$ or $N_A$) in the silicon active region :
$$R_c \propto \exp\left(\frac{4\pi\Phi_B}{h}\sqrt{\frac{\varepsilon_s m^*}{N}}\right)$$
where:
- $h$ is Planck's constant (Engineering Practice),
- $\varepsilon_s$ is the semiconductor permittivity ,
- $m^*$ is the effective mass of the charge carriers ,
- $N$ is the active doping concentration .
To minimize $R_c$, the silicide's work function must be aligned closely with the conduction band edge for n-type contacts or the valence band edge for p-type contacts [P3, T2]. Pure $NiSi$ has a mid-gap work function, which is moderately effective for both carrier types but not optimal for sub-10 nm nodes .
The introduction of platinum, which possesses a higher work function than nickel, causes the effective work function of the resulting ternary $Ni_{1-x}Pt_xSi$ to shift toward the valence band edge . This work function tuning significantly reduces the Schottky barrier height for p-type source/drain contacts, enhancing hole injection efficiency [P3, T2]. At the same time, the highly doped contact region ensures that the depletion width ($W_{dep}$) is minimized, maximizing the probability of carrier tunneling through the remaining barrier .
Process Principles
Integrating NiPt into a manufacturing process flow requires precise, directional control over key physical parameters to balance phase stability, electrical performance, and physical integrity (Engineering Practice).
Platinum Concentration and Work Function Balancing
The atomic fraction of platinum in the deposited NiPt alloy is a critical process variable [P2, P3]. Increasing the platinum concentration directionally enhances the thermal stability of the monosilicide phase, raising the temperature threshold at which the film agglomerates or converts to $NiSi_2$ [P2, P3].
However, this thermal security comes at a cost: because platinum silicide ($PtSi$) has a slightly higher bulk resistivity than nickel monosilicide ($NiSi$), increasing the platinum content beyond a optimal threshold directionally increases the overall sheet resistance ($R_s$) of the contact film . Furthermore, for n-type transistors, excess platinum shifts the work function too close to the valence band, which can increase the Schottky barrier height for electrons and degrade n-channel performance [P3, T2]. Therefore, the platinum fraction must be carefully balanced to meet both thermal budget and contact resistance targets (Engineering Practice).
Thermal Budget and Multi-Step Annealing Kinetics
The kinetics of the solid-phase reaction are primarily governed by the thermal budget (temperature and duration) applied during rapid thermal annealing (RTA) [P2, P3]. In modern integration, a two-step RTA scheme is typically employed to control the reaction pathway and prevent defect formation (Engineering Practice):
- RTA-1 (First Anneal): This low-temperature step is designed to drive the interdiffusion of nickel and silicon to form the metal-rich silicide phase ($Ni_2Si$) . Applying too high of a thermal budget during RTA-1 can lead to excessive lateral diffusion of nickel atoms, causing lateral encroachment underneath the gate spacer and leading to junction leakage . Conversely, insufficient thermal budget results in incomplete reaction, leaving excess unreacted metal that is subsequently lost during the wet etch step (Engineering Practice).
- Selective Wet Etch: Following RTA-1, a selective wet chemical etch is performed to remove the unreacted NiPt from the dielectric isolation regions (such as silicon dioxide or silicon nitride) without damaging the newly formed silicide or the silicon substrate [A1, A2]. This step relies on acid-peroxide mixtures, where the etching selectivity between the unreacted metal and the silicide is critical .
- RTA-2 (Second Anneal): A second thermal treatment is performed at an elevated temperature to transform the metal-rich phase into the highly conductive monosilicide phase ($NiSi$) [P2, P3]. The thermal budget of RTA-2 must be high enough to complete the phase transformation, but must not exceed the threshold where the silicide undergoes agglomeration or converts to the high-resistance $NiSi_2$ phase [P2, P3].
Substrate Influence and Surface Preparation
The quality of the starting silicon surface and its crystalline structure strongly influence the NiPt reaction kinetics . Crystalline silicon substrates ($Si(001)$) exhibit different diffusion rates and interfacial alignment characteristics compared to polycrystalline silicon or amorphous silicon regions [P2, P3].
Additionally, high-dose ion implantation of dopants (such as arsenic, phosphorus, or boron) in the source/drain regions alters the local silicon lattice structure, introducing point defects and changing the chemical potential of the system [T1, T2]. Heavily doped substrates can retard the diffusion of nickel, requiring a slightly increased thermal budget to achieve complete monosilicide conversion, while simultaneously increasing the risk of dopant segregation at the silicide-silicon interface [P3, T2].
Challenges & Failure Modes
As device geometry continues to shrink, several physical mechanisms can compromise the structural and electrical integrity of NiPt contacts (Engineering Practice).
Thermal Agglomeration and Grain Boundary Grooving
Thin silicide films are inherently meta-stable structures . At elevated temperatures, the system attempts to minimize its total surface and interfacial energy . This thermodynamic driving force manifests as grain boundary grooving, where the contact film begins to pinch off along grain boundaries, eventually breaking up into isolated islands of silicide .
This morphological degradation, known as agglomeration, leads to a catastrophic increase in sheet resistance and contact resistance . Because the driving force for agglomeration is inversely proportional to the film thickness, this failure mode becomes exponentially more severe in advanced nodes where the contact film is extremely thin [P2, P3].
[Uniform Thin NiPt Silicide Film]
===============(Metal)===============
───────────────(Interface)───────────
###############(Silicon)#############
│
▼ (Excess Thermal Exposure / Agglomeration)
===(Islands)=== ===(Islands)===
─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─
###############(Silicon)############# <-- Discontinuous contact / High Rs [P3]
Lateral Encroachment and Junction Spiking
During the initial solid-phase reaction, nickel is the dominant diffusing species, moving rapidly into the silicon substrate to react with Si atoms . If the native oxide is non-uniformly removed or if the RTA-1 thermal budget is poorly controlled, nickel can undergo rapid, localized lateral diffusion .
This lateral migration allows nickel to penetrate underneath the gate dielectric and spacer oxide, a phenomenon known as lateral encroachment or "silicide piping" . If the nickel penetrates into the depletion region of the PN junction, it introduces deep-level trap states within the bandgap, leading to severe junction leakage currents and, in worst-case scenarios, a direct gate-to-channel short circuit .
Phase Degradation to Disilicide
In thin-film configurations, the thermodynamic window for stable monosilicide ($NiSi$) formation is narrow [P2, P3]. If the subsequent back-end-of-line (BEOL) thermal processing exceeds the thermal stability limits of the NiPt silicide, the film will transition to the disilicide ($NiSi_2$) phase [P2, P3].
Because $NiSi_2$ consumes approximately twice as much silicon per unit of metal reacted compared to $NiSi$, this phase transformation causes the silicide interface to consume the shallow source/drain junctions, resulting in severe leakage currents or complete junction breakdown [P3, T2].
Pt Segregation and Resistance Spikes
During the solid-phase reaction, platinum does not diffuse as rapidly as nickel . As the reaction front moves forward, platinum tends to segregate toward the moving silicide-silicon interface or accumulate near the surface .
While a controlled accumulation of platinum at the interface can be beneficial for reducing the Schottky barrier height, non-uniform segregation can lead to the formation of localized, high-resistance ternary phases or structural defects at the contact interface, manifesting as contact resistance spikes across the wafer .
Technology Node Evolution
The implementation and integration of NiPt silicide have evolved significantly to meet the requirements of changing transistor architectures and scaling nodes .
28nm Node: Planar Integration
During the 28nm Planar Flow, transistors featured a planar architecture where the source, drain, and gate regions were co-planar . In this node, NiPt silicide was adopted to replace cobalt silicide ($CoSi_2$) to prevent high contact resistance on narrow lines .
The primary challenge was ensuring uniform PVD deposition of the NiPt alloy across the planar active areas and managing the thermal budget of subsequent dielectric depositions to prevent the monosilicide from transitioning to the disilicide phase [P2, P3].
14nm Node: The Transition to 3D FinFETs
With the introduction of the 14nm FinFET architecture, contact engineering entered the three-dimensional realm . The source and drain regions were now raised, epitaxial silicon or silicon-germanium fins (Engineering Practice).
This 3D geometry presented severe challenges for conventional PVD sputtering of NiPt, as shadow effects and directional deposition resulted in non-uniform coverage on the sidewalls of the narrow fins .
Furthermore, the integration of contact-on-active-gate (COAG) schemes required the formation of self-aligned contacts in extremely confined spaces, making the control of lateral nickel encroachment critical to prevent gate-to-contact shorting .
7nm Node and Beyond: Ultra-Thin Films and Backside Power Delivery
At the 7nm FinFET node and beyond (including nanosheet and gate-all-around architectures), the contact dimensions scaled to sub-10 nm regimes [P2, A1]. At these scales, the physical mechanics of the solid-phase reaction change, as the system bypasses intermediate phases and is highly susceptible to low-temperature $NiSi_2$ formation .
To maintain low contact resistance, the thickness of the NiPt silicide liner must be kept to a minimum, requiring advanced interfacial treatments and highly controlled atomic-scale deposition [P1, A1].
Furthermore, modern architectures are moving toward backside power delivery networks (BSPDN) to reduce IR drop and maximize front-side routing density . In these advanced schemes, backside contacts and backside power bars are formed through the wafer backside [A1, A2]. This requires the deposition of highly conformal silicide liners, such as NiPt, inside high aspect ratio vias from the backside to connect directly to the active source/drain and gate regions [A1, A2].
| Technology Node | Device Architecture | Primary NiPt Integration Challenge | Key Process Solution |
|---|---|---|---|
| 28nm | Planar | Sheet resistance scaling on narrow lines | Adoption of NiPt to replace $CoSi_2$ |
| 14nm | FinFET | Non-uniform coverage on 3D fin sidewalls | Conformal PVD process optimization (Engineering Practice) |
| 7nm | FinFET / Nanosheet [P2, A1] | Extreme scaling, phase sequence changes | Ultra-thin NiPt liners and optimized RTA [P2, A1] |
| 3nm & Beyond | Nanosheet / BSPDN | Backside via and high aspect ratio contact fill [A1, A2] | Chemical/Atomic vapor deposition of NiPt [P1, A1] |
Related Processes
The formation of a stable, low-resistance NiPt contact is highly dependent on several closely integrated upstream and downstream process steps (Engineering Practice).
Surface Pre-cleaning
Before the NiPt alloy can be deposited, the native silicon dioxide layer on the active areas must be completely removed . Any remaining oxide acts as a physical diffusion barrier, preventing the uniform reaction of nickel and silicon and leading to localized unreacted spots or high-resistance contacts .
This is typically accomplished using dilute hydrofluoric acid (DHF) wet etching or advanced dry chemical vapor cleans, which selectively remove the native oxide while leaving the surrounding dielectric spacers intact (Engineering Practice).
Barrier and Capping Layers
Immediately following the PVD deposition of the NiPt alloy, an in-situ capping layer, typically titanium nitride (TiN), is deposited over the metal film [A1, A2].
This capping layer serves two critical functions: first, it prevents the underlying nickel from oxidizing when exposed to ambient oxygen during the transfer to the RTA chamber; second, it acts as a mechanical confinement layer during the rapid thermal anneal, applying compressive stress that helps suppress morphological agglomeration and controls the direction of metal diffusion [A1, A2].
Contact Plug Metallization
Once the NiPt silicide is formed and the unreacted metal is removed, the remaining contact trench must be filled with a low-resistance metal plug to route the signal to the first metal layer [A1, A2]. This step requires the deposition of a liner layer followed by a void-free fill process [A1, A2].
Historically, tungsten (W) was the material of choice; however, in advanced nodes, cobalt (Co) or ruthenium (Ru) are increasingly used due to their lower resistance and superior electromigration performance in high aspect ratio contact trenches [A1, A2].
Future Outlook
As the semiconductor industry progresses toward atomic-scale manufacturing and novel channel materials, the role of NiPt is expanding and adapting to meet new material and structural demands (Engineering Practice).
Transition to Atomic Layer Deposition (ALD)
While physical vapor deposition (PVD) has been the industry standard for depositing NiPt alloys, its line-of-sight nature makes it increasingly difficult to achieve uniform step coverage in high aspect ratio features and complex 3D nanosheet architectures [P1, A1].
To overcome this, significant research is focused on developing atomic layer deposition (ALD) processes for NiPt [P1, A1]. ALD relies on sequential, self-limiting surface chemical reactions to deposit conformal, atomic-scale films even within highly complex, high-surface-area structures, ensuring uniform silicide thickness and suppressing void formation .
Alternative Co-Alloying Schemes
While platinum remains the primary alloying element for stabilizing nickel silicide, researchers are actively exploring ternary and quaternary alloy configurations [P2, P3].
By introducing co-dopants such as cobalt (Co), aluminum (Al), or rare-earth elements alongside platinum, engineers can decouple the thermal stability benefits from the work function shifts, allowing for independent optimization of the contact work function for n-type and p-type regions while maintaining high thermal resilience [P2, P3].
Integration with 2D Semiconductors
Looking beyond silicon, the integration of two-dimensional (2D) semiconductors, such as transition metal dichalcogenides (e .g., $MoS_2$ or $WSe_2$), represents the next frontier in channel scaling (Engineering Practice).
Forming reliable, low-resistance Ohmic contacts to these atomically thin 2D layers is exceptionally challenging due to the lack of dangling bonds and the risk of severe metal-induced gap states (Engineering Practice).
Modified low-temperature NiPt metallization and novel deposition strategies are being studied as potential pathways to create clean, van der Waals-like contacts on 2D surfaces, enabling the continued evolution of high-performance logic devices .