Mastering Void-Free Fill in Advanced Semiconductor Manufacturing: Physical Principles, Process Engineering, and Node Evolution

Introduction

In modern ultra-large-scale integration (ULSI) complementary metal-oxide-semiconductor (CMOS) fabrication, the ability to seamlessly deposit materials into high-aspect-ratio (HAR) features is a cornerstone of device performance and reliability. This process, collectively referred to as gap fill (or gap-fill), is highly critical when isolating active regions or establishing electrical interconnects. As device scaling continues to shrink lateral dimensions, the aspect ratios of isolation trenches and metal vias increase exponentially, making trench fill increasingly difficult.

The primary objective of these processes is to achieve a completely void-free fill. A void is an undesirable physical cavity or empty space trapped within a filled trench or via. In shallow trench isolation (STI) applications, the presence of a void is often associated with a weak material seam. During subsequent manufacturing steps, such as wet etching or chemical mechanical planarization (CMP), these seams can be exposed and preferentially etched, creating open paths. If subsequent gate electrode materials, like polysilicon or metals, deposit into these opened seams, they form conductive filaments that cause catastrophic electrical short-circuits between adjacent active zones.

To prevent such device failures, process engineers must understand the fundamental physical and chemical mechanisms that govern material transport and deposition. Achieving void-free gap fill requires precise control over precursor chemistry, plasma-surface interactions, electrochemical kinetics, and advanced profile-shaping methodologies.

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Physics & Mechanism

The physics of filling a sub-micron or nanometer-scale trench depends heavily on whether the deposition process is driven by gas-phase reactions, plasma-assisted physical transport, or liquid-phase electrochemical reactions.

Gas-Phase Transport and Shadowing Effects

In conventional thermal chemical vapor deposition (CVD) processes, such as low-pressure chemical vapor deposition (LPCVD) or sub-atmospheric chemical vapor deposition (SACVD), precursors diffuse from the bulk gas phase to the wafer surface. The transport of species within a narrow trench is governed by the sticking coefficient (the probability that a reactive species adsorbs and reacts upon colliding with the surface) and the arrival angle distribution.

For processes with high sticking coefficients, molecules react almost immediately upon contact with the upper corners of the trench. This leads to a severe shadowing effect, where the top corners of the trench receive a significantly higher flux of precursors than the bottom and sidewalls. Consequently, the top corners grow faster and eventually merge (pinch off), trapping a large void in the center of the trench. While low sticking coefficients of CVD processes help with filling, the shadowing effects are still important and voids can still form for high aspect ratio structures [T1]. Conversely, reducing the sticking coefficient allows precursors to undergo multiple non-reacting collisions, bouncing off the sidewalls and diffusing deeper into the trench to yield more conformal profiles. However, even with low sticking coefficients, physical shadowing persists in high-aspect-ratio trenches, ultimately leading to void formation if left unmitigated.

High-Density Plasma CVD (HDPCVD)

To overcome the physical scaling limits of standard PECVD and LPCVD, high-density plasma (HDP) CVD is utilized. The core mechanism of HDPCVD is the simultaneous occurrence of chemical vapor deposition and physical sputter etching.

HDPCVD systems generate a highly directed, anisotropic ionic flux perpendicular to the wafer surface. This directed ion flux delivers energy to the bottom of the trench, promoting localized deposition. Concurrently, an angle-dependent sputtering action occurs at the top corners of the trench. Sputtering rates of silicon dioxide ($SiO_2$) and similar materials peak at oblique angles. As deposition material begins to build up and form an overhang at the top corners of the trench, the high-angle ion bombardment preferentially sputters this material away. This continuous dep-etch mechanism keeps the trench mouth open, preventing shadowing and enabling complete, void-free bottom-up gap fill.

Electrochemical Deposition (ECD) and Superfilling

For copper metallization in back-end-of-line (BEOL) structures, gas-phase deposition is replaced by liquid-phase electrochemical deposition (ECD). The back end of the line (BEOL) copper (Cu) interconnect line width and spacing is decreasing with each advancement in technology node [P1]. To achieve void-free filling of narrow copper lines, a mechanism known as superfilling or bottom-up filling is required. This behavior is achieved by adding a multicomponent organic additive package to an acidic copper sulfate electrolyte. This package typically consists of:

1. Suppressors / Inhibitors: Typically high-molecular-weight polymers like polyethylene glycol (PEG) that, in the presence of chloride ions ($Cl^-$), adsorb strongly onto the top surfaces and upper sidewalls of the trenches, inhibiting copper ion reduction.
2. Accelerators / Catalysts: Small, sulfur-containing molecules such as bis(3-sulfopropyl) disulfide (SPS) that lower the overpotential for copper deposition, accelerating the growth rate.
3. Levelers: Nitrogen-containing cationic organic compounds, such as Janus Green B (JGB), which preferentially adsorb at high-current-density regions (like the trench entrance) to suppress localized overgrowth.

During the initial phase of electroplating, all additives adsorb onto the trench surfaces. As copper deposition begins, the surface area at the bottom of the narrow trench rapidly decreases due to the concave geometry. This reduction in surface area causes the local surface concentration of the accelerator (SPS) to increase significantly because of a convective accumulation effect. Meanwhile, the bulkier suppressors (PEG) and levelers (JGB) are transport-limited and cannot quickly diffuse into the deep, narrow trench. Consequently, the deposition rate at the trench bottom becomes orders of magnitude faster than at the top surfaces, leading to rapid bottom-up growth that completely eliminates voids.

To mathematically analyze and screen these additive interactions, electrochemical methods such as linear sweep voltammetry (LSV), chronoamperometry (CA), and cyclic voltammetric stripping (CVS) are employed. The effective surface coverage ($u_{eff}$) of the suppressing additive system can be quantitatively defined as:

$$u_{eff} = 1 - \frac{i_{additive}}{i_{no}}$$

Where:

• $i_{no}$ represents the current density measured in an electrolyte free of suppressing additives ($A \cdot cm^{-2}$).
• $i_{additive}$ represents the current density in the presence of the suppressing additives ($A \cdot cm^{-2}$).
• $u_{eff}$ represents the dimensionless effective surface coverage, which directly correlates with the suppression efficiency and the resulting bottom-up filling capability.

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Process Principles

The boundary between void-free filling and catastrophic void creation is determined by the directional interaction of key process parameters. Understanding these parameter trajectories allows process engineers to optimize deposition recipes for varying aspect ratios and trench geometries.

Plasma Deposition Parameter Dynamics

In plasma-enhanced deposition systems, such as those used for depositing undoped silicate glass (USG) or carbon-doped low-k films, the balance between deposition and sputtering is highly sensitive to power configurations:

• RF Bias Power / Ion Energy: Increasing the high-frequency bias power applied to the electrostatic chuck increases the directional kinetic energy of the incoming ions. This enhances the sputter-etching rate of the corner overhangs, helping to keep the trench open. However, if the bias power is set too high, it can induce severe physical damage to the silicon substrate or the underlying liner oxides, leading to enhanced junction leakage and reduced gate oxide reliability.
• Precursor Flow Ratio: The ratio of the deposition precursor (e.g., silane or tetraethyl orthosilicate (TEOS)) to the sputtering gas (typically argon or helium) directionally shifts the process between deposition-dominated and etch-dominated regimes. Higher precursor-to-sputter gas ratios increase the net deposition rate but compress the gap-fill window by promoting rapid top corner pinch-off.
• RF Power Duty Cycle Modulation: Advanced gap-fill tools implement dual-power radio frequency (RF) duty-cycle modulation. In the high-RF-power phase, aggressive anisotropic etching removes material from the top corners of the trench. In the low-RF-power phase, chemical deposition dominates, allowing material to accumulate inside the trench. By modulating the duty cycle—defined by the ratio of the high-power duration ($t_1$) to the low-power duration ($t_2$)—engineers can balance top corner etching and trench filling to achieve uniform, void-free results across features of varying critical dimensions (CD).

Chemical and Thermal Parameter Dynamics

In thermal CVD processes, such as the SACVD of oxides using ozone ($O_3$) and TEOS, temperature and pressure dictate the surface reaction kinetics:

• Deposition Temperature: Increasing the substrate temperature enhances the surface mobility of adsorbed species, enabling them to migrate further down the sidewalls toward the bottom of the trench. However, excessively high temperatures can also accelerate the gas-phase reaction rate, increasing the sticking coefficient and leading to poorer step coverage and void formation.
• Ozone-to-TEOS Ratio: In $O_3$-TEOS processes, the $O_3$ flow rate directly influences the film's step coverage and chemical densification. An optimized, high $O_3$:TEOS ratio promotes a highly mobile, polymer-like intermediate state on the wafer surface, which flows into high-aspect-ratio trenches to provide excellent gap-fill performance. However, these films are highly sensitive to the underlying substrate material (substrate sensitivity), which can degrade deposition rates and film density in narrow trenches.

Electrochemical Parameter Dynamics in Copper ECD

For electrochemical filling, the process trajectory is governed by electrical bias, rotation speed, and additive concentration:

• Cathodic Current Density: Depositing at a lower initial current density minimizes the deposition rate at the trench corners, preventing premature pinch-off. Once bottom-up superfilling is established, the current density can be increased to rapidly build up the copper overburden.
• Wafer Rotation Speed: In a rotating disk electrode (RDE) configuration, high rotation speeds reduce the hydrodynamic boundary layer thickness. This increases the convective transport of bulkier, mass-transport-limited additives (like JGB and PEG) to the top surfaces of the wafer, enhancing the suppression of top-surface growth while leaving the trench bottom highly active for copper growth.

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Challenges & Failure Modes

Achieving a void-free fill is a delicate balancing act. Deviations in upstream etch profiles, material interactions, or deposition parameters can trigger severe failure modes.

       [ Overhang Pinch-Off ]                     [ Centrally Symmetric Void ]
           
             /=========\                                 /=========\
            /  _     _  \                               /  |     |  \
           |  ( )   ( )  |  <-- Overhang              |   |     |   |
           |   \     /   |      Pinch-off           |   |     |   |
           |    |   |    |                          |   |     |   |
           |   /     \   |                          |   |  O  |   | <-- Trapped
           |  |       |  |                          |   |     |   |     Void
           |  |____|  |                          |   |_____|   |
           \____/                          \____/

Premature Top Sealing and Overgrowth Pinch-Off

The most common physical failure mode is premature top sealing, which occurs when the deposition rate at the top corners of a trench or via exceeds the transport and deposition rate at the bottom. This is driven by high precursor sticking coefficients, physical shadowing, or inadequate sputter-etching in plasma systems. Once the top of the trench pinches off, reactants can no longer enter, trapping a large, gas-filled void inside the structure.

Centrally Symmetric Voids in Electroplating

In copper ECD, if the organic additive chemistry is unbalanced, a centrally symmetric void can form along the centerline of the trench. This occurs if the concentration of the accelerator (SPS) is insufficient to overcome the suppressor (PEG) at the trench bottom, or if the leveler (JGB) concentration is too high, completely shutting down the bottom-up growth mechanism. The trench then fills conformally from the sidewalls inward, inevitably trapping a seam or a long, continuous void in the center.

Thermal Stress and Shrinkage-Induced Defects

Many gap-fill materials, such as spin-on dielectrics, flowable oxides, or $O_3$-TEOS oxides, are deposited in a highly porous, low-density state. To stabilize these films, a high-temperature post-deposition densification anneal is required. During this annealing process, the film undergoes significant volumetric shrinkage.

Because the oxide is constrained by the rigid silicon trench sidewalls, this shrinkage introduces massive tensile stress onto the underlying silicon substrate. If the stress exceeds the plastic deformation limit of silicon, it creates crystalline defects and dislocations, particularly in heavy-dose arsenic-implanted source-drain regions. These defects act as generation-recombination centers, leading to a massive increase in junction diode leakage currents.

Trench Corner Degradation and Field Concentration

During HDPCVD or high-bias etching, the physical sputtering component can damage the sensitive corners of the active silicon trenches. If the oxide liner is too thin or damaged, the subsequent gate oxide grown over these corners will be thin and non-uniform.

From device physics, the electric field distribution around a sharp corner is governed by the Poisson equation. Sharp, damaged corners cause severe local electric field concentration, which lowers the threshold voltage locally and creates a parasitic transistor channel. This parasitic conduction manifests as a distinct double-hump or double-peak phenomenon in the subthreshold $I_{ds}-V_{gs}$ curve. Furthermore, the field concentration degrades the charge-to-breakdown ($Q_{bd}$) of the gate dielectric, leading to premature device wear-out and reliability failures.

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Technology Node Evolution

The engineering strategies used to achieve void-free fill have undergone radical transformations as the semiconductor industry transitioned through planar and 3D transistor architectures.

+-----------------------------------------------------------------------------------------+
|                                 TECHNOLOGY NODE EVOLUTION                               |
+-----------------------------------------------------------------------------------------+
|  28nm Node (Planar)        |  14nm Node (FinFET)         |  7nm & Beyond (HAR FinFET/GAA) |
+----------------------------+-----------------------------+------------------------------+
| * SACVD (TEOS-O3) limits   | * FCVD (Flowable Oxides)    | * Extreme aspect ratios      |
| * Linear profile limits    | * High aspect ratios        | * Alternative metals         |
| * L-E-G downstream etch    | * Low thermal budget        | * Advanced ALD & selective   |
|   reshaping (NH3/NF3)      | * Spin-on Dielectrics (SOG) |   bottom-up fills            |
+-----------------------------------------------------------------------------------------+

28nm Node: Reshaping with Liner-Etch-Gap-Fill (L-E-G)

At the 28nm Planar Flow node, the aspect ratios of STI structures reached a point where conventional SACVD $SiO_2$ struggled to achieve reliable, void-free gap fill due to increasingly vertical sidewalls. To address this, engineers introduced the Liner-Etch-Gap-fill (L-E-G) strategy.

This process begins by depositing a thin, conformal $SiO_2$ liner using SACVD. Next, an innovative in-situ etch-back step is performed using a downstream plasma of ammonia ($NH_3$) and nitrogen trifluoride ($NF_3$). The active neutral species react with the oxide liner to form a solid ammonium salt layer, ammonium hexafluorosilicic salt:

$$(NH_4)_2SiF_6$$

This reaction is self-limiting because the diffusion of active species is restricted by the growing salt layer. Subsequently, a mild thermal treatment sublimates the salt layer, leaving behind a highly controlled, gently sloped liner profile. This slope-reshaping step widens the mouth of the trench, enabling a subsequent SACVD step to complete the gap fill without forming voids.

14nm Node: The FinFET Revolution and Flowable Oxides

With the transition to the 14nm FinFET architecture, the aspect ratios of the trenches between dense silicon fins increased drastically. At these extreme aspect ratios, physical line-of-sight deposition methods like HDPCVD and conventional SACVD are unusable because they pinch off almost instantly.

To resolve this, the industry adopted Flowable Chemical Vapor Deposition (FCVD) and advanced spin-on glass (SOG) materials, such as undoped silicate glass (USG) and phosphosilicate glass (PSG). FCVD processes introduce silicon-containing precursors (such as trisilylamine) and radical co-reactants (like ammonia or oxygen radicals) into the chamber at low temperatures. The precursors react to form a highly fluid, polymer-like liquid oligomer film on the wafer surface. Driven by capillary forces, this liquid film flows down and fills the narrowest gaps between fins from the bottom up, ensuring a completely seamless, void-free fill. A subsequent steam curing and thermal treatment densifies the liquid film into a high-quality silicon dioxide layer.

7nm Node and Beyond: Alternative Metals and Extreme Aspect Ratios

At the 7nm FinFET node and beyond, scaling challenges shifted focus toward BEOL metal lines and contact trench fill. Barrier with Co/Ru liner are reported to reduce line/via resistance and improve interface quality and reliability as required in advanced technology nodes [P2]. As the critical dimensions of contact vias shrank, conventional copper metallization faced severe physical limitations. The thin physical vapor deposition (PVD) copper seed layers required for electroplating suffer from poor step coverage, leading to seed discontinuous defects and subsequent plating voids.

To overcome this, the industry integrated alternative metals like cobalt and ruthenium for contact and local interconnect trench fill. These metals can be deposited using highly conformal atomic layer deposition (ALD) or metal-organic chemical vapor deposition (MOCVD) with ultra-thin liner configurations, maximizing the conductive volume of the trench.

Furthermore, because these advanced nodes operate under severe subthreshold current leakage constraints, any structural defect or void in the isolation oxide can lead to uncontrollable off-state leakage. The subthreshold drain-source current ($I_{ds}$) and subthreshold swing ($S$) are governed by:

$$I_{ds} \propto \exp\left(\frac{q V_{gs}}{\eta kT}\right)$$

$$S = \eta \cdot \frac{kT}{q} \ln(10)$$

Where:

• $V_{gs}$ is the gate-source voltage ($V$).
• $q$ is the elementary electron charge ($C$).
• $k$ is the Boltzmann constant ($J \cdot K^{-1}$).
• $T$ is the absolute temperature ($K$).
• $\eta$ is the subthreshold slope factor.

To maintain an acceptable ratio between the drive current ($I_{on}$) and leakage current ($I_{off}$), $\eta$ must be kept as close to 1.0 as possible. Voids in the surrounding isolation dielectrics degrade electrostatic gate control and increase capacitive coupling, driving up the subthreshold swing and causing massive static power dissipation. This highlights why achieving absolute void-free fill is a critical requirement for modern low-power mobile and high-performance computing chips.

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Related Processes

Void-free gap fill is highly dependent on upstream and downstream process steps. The entire integration flow must be co-optimized to ensure structural integrity and electrical yield.

Lithography and Anisotropic Etching

The geometry of the trench is determined by lithography (often using deep ultraviolet (DUV) immersion or extreme ultraviolet (EUV) lithography) and subsequent anisotropic dry etching. The trench sidewall profile must be carefully managed; a steep, tapered sidewall angle is ideal. If the etch process produces re-entrant profiles (where the trench is wider at the middle than the top), achieving a void-free fill with standard CVD is mathematically impossible due to shadow effects.

Wet Clean and Surface Conditioning

Prior to material deposition, the patterned trenches must undergo a rigorous wet clean process to remove organic residues, native oxides, and etching polymers. Hydrofluoric acid (HF) is typically used to clean the silicon interface. However, if the HF dip is too aggressive, it can undercut the pad oxide beneath the silicon nitride hard mask, creating a horizontal micro-gap. This undercut profile acts as a precursor trap, leading to micro-voids during the subsequent gap-fill step.

Chemical Mechanical Planarization (CMP)

Following the gap-fill process, the wafer surface is covered with a highly non-uniform overburden of the deposited material. CMP is used to polish back this excess overburden, stopping precisely on the underlying hard mask (e.g., silicon nitride). CMP is highly sensitive to pattern density. If the gap-fill film is non-uniform or contains weak, un-densified seams, the mechanical downforce and chemical slurry of the CMP process can cause local tearing, peeling, or severe dishing, exposing the underlying active regions and ruining the device yield.

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Future Outlook

As the semiconductor industry transitions to Gate-All-Around (GAA) nanosheets, Complementary FET (CFET), and 3D DRAM architectures, gap-fill requirements are reaching the atomic scale.

                                  [ GAA / CFET ERA ]
                             
                                   |  |  |  |  |  |
                                   |  |  |  |  |  |
                                  /===============\
                                 |  [ALD Precursor] | <-- True atomic scale
                                 |   Selective      |     bottom-up growth
                                 |   Bottom-Up      |
                                 |   Deposition     |
                                  \===============/
                                   |  |  |  |  |  |

The future of void-free fill lies in Selective Bottom-Up Atomic Layer Deposition (ALD). By utilizing self-assembled monolayers (SAMs) or specialized surface-treatment co-flows, process engineers can selectively deactivate the top surfaces and upper sidewalls of nanometer-scale trenches. This allows the ALD precursor to react exclusively at the bottom of the trench, enabling a true atom-by-atom bottom-up fill with absolute selectivity and zero void formation.

Additionally, in advanced system-in-package (SiP) and 3D packaging technologies, void-free fill is expanding into micro-scale glass packaging substrates. Utilizing high-aspect-ratio cavities etched in glass with inclined sidewalls helps manage mechanical and thermal stresses. The gaps between the embedded components and glass sidewalls are filled using vacuum lamination of advanced polymer films, such as Ajinomoto build-up film (ABF), epoxy molding compound (EMC), or modified polyimide (MPI), to achieve robust mechanical support and reliable electrical routing.