Undoped Silicate Glass (USG) in Semiconductor Manufacturing: Principles, Mechanical Reliability, and Process Integration

Introduction

Undoped silicate glass (USG) is one of the most foundational thin-film dielectric materials in modern semiconductor manufacturing [T1]. At its core, USG is a high-purity amorphous silicon dioxide (SiO2) film deposited without the deliberate introduction of dopants such as boron or phosphorus [T1, A1]. In contrast to doped glasses like borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG), which are intentionally engineered with impurities to lower thermal reflow temperatures or getter mobile ionic contaminants, USG remains chemically pure and structurally robust [T1]. This fundamental material purity makes USG an indispensable component across a wide variety of front-end-of-line (FEOL) and back-end-of-line (BEOL) processes (Engineering Practice).

Historically, USG has served critical roles in electrical isolation, passivation, and stress engineering (Engineering Practice). In FEOL integration, it is widely utilized to form the shallow trench isolation (STI) structures that electrically isolate adjacent active devices on the silicon substrate [A2]. In BEOL metallization, USG acts as a crucial passivation layer [A1], a diffusion barrier to prevent moisture and impurity ingress [T1], and a mechanical support layer during intensive planarization steps [P1]. As device architectures transitioned from planar logic elements to complex three-dimensional geometries, understanding the physical, mechanical, and chemical properties of USG has become vital for maintaining high chip yield and device reliability [P1, T3].

Physics & Mechanism

The unique properties of undoped silicate glass (USG) stem directly from its microscopic chemical structure and bonding physics [T1]. Like thermal silicon dioxide, USG is comprised of a continuous random network of silicon-oxygen (Si-O) tetrahedra, where each silicon atom is covalently bonded to four oxygen atoms in a non-periodic, amorphous arrangement [T1, T2]. Because it lacks intentional dopant species such as phosphorus or boron, the USG network does not suffer from the network-disrupting effects that occur when trivalent or pentavalent atoms replace tetravalent silicon [T1]. Consequently, USG possesses a higher density and a stronger, more continuous network of covalent bonds than its doped counterparts (Engineering Practice).

This continuous network translates directly into superior mechanical properties (Engineering Practice). According to nanoindentation characterizations using continuous stiffness measurement (CSM), USG exhibits an elastic modulus of approximately 79.06 to 80.66 GPa and a hardness ranging from 5.65 to 7.52 GPa [P1]. This is significantly higher than organosilicate glass (OSG) or carbon-doped oxide (SiOCH) low-k dielectric materials, whose elastic moduli typically range from 2 to 14 GPa and hardness from 0.5 to 7 GPa due to the deliberate introduction of organic methyl groups and porosity [P1, P2]. The high network density of USG also determines its dielectric constant (k-value), which is approximately 4.1 [P2]. While this dielectric constant is higher than that of fluorinated silicate glass (FSG, k ≈ 3.7) or porous SiOCH (k ≈ 2.9), the mechanical integrity of USG makes it far less susceptible to mechanical cracking, interface delamination, and elastoplastic deformation during chemical mechanical planarization (CMP) or advanced packaging thermal cycles [P1, P2].

The physical mechanism of USG deposition involves gas-phase chemical reactions and subsequent surface adsorption and diffusion (Engineering Practice). When deposited via plasma-enhanced chemical vapor deposition (PECVD) or atmospheric pressure chemical vapor deposition (APCVD), precursor molecules undergo decomposition to form active radicals [P2, T1]. For instance, when using tetraethyl orthosilicate (TEOS) with ozone (O3), the reaction is highly driven by the surface adsorption of intermediate silanol species, which diffuse along the substrate surface to find low-energy sites, resulting in highly conformal film coverage [T1]. However, because these reactions are carried out at relatively low thermal budgets compared to high-temperature thermal oxidation, USG films inherently retain some level of sub-stoichiometric species, silanol (Si-OH) bonds, and adsorbed moisture within their amorphous networks [T1].

Process Principles

The final material properties of USG are highly sensitive to the deposition parameters and chemical pathways chosen during the fabrication process (Engineering Practice). USG can be deposited through several chemical vapor deposition (CVD) techniques, including low-pressure chemical vapor deposition (LPCVD), APCVD, and PECVD, each utilizing distinct precursor chemistry and excitation mechanisms [T1].

The two most common chemical precursor systems for USG are silane (SiH4) and tetraethyl orthosilicate (TEOS) [T1].

Precursor Chemistry Comparison

• Silane-Based Deposition: In silane-based CVD, silane reacts with oxygen (O2) or nitrous oxide (N2O) at relatively low temperatures [T1]. The reaction proceeds rapidly in the gas phase, which can sometimes lead to poor step coverage over high-aspect-ratio (HAR) features due to the high mass-transport-limited deposition rate of reactive radicals (Engineering Practice).
• TEOS-Based Deposition: TEOS-based CVD, especially when combined with ozone (O3) at moderate thermal budgets, relies on a surface-reaction-limited mechanism [T1]. The adsorbed TEOS fragments possess high surface mobility, which allows them to migrate deep into narrow trenches before reacting, providing exceptional step coverage and conformality [T1]. However, a key trade-off of the TEOS/O3 reaction is that the resulting USG films can be highly porous and prone to absorbing moisture if the process parameters are not precisely balanced [T1].

Directional Parameter Interactions

Several key factors directionally influence the quality, density, and stress of the deposited USG film:

• Temperature: Increasing the deposition or post-deposition annealing temperature accelerates film densification, driving out residual silanol groups and moisture, which reduces the dielectric constant back toward its ideal value of 4.1 and lowers wet etch rates in hydrofluoric acid solutions [T1].
• RF Power (in PECVD): Raising the radio-frequency (RF) power increases ion bombardment during film growth, which physically compacts the depositing layer, increasing both the density and compressive stress of the USG film while reducing its susceptibility to moisture absorption [P2].
• Precursor Ratio: In TEOS/O3 processes, increasing the ozone-to-TEOS ratio generally enhances the oxidation state and chemical purity of the film, but excessive ozone can sometimes accelerate gas-phase nucleation, leading to particle contamination and degradation of step coverage (Engineering Practice).

Challenges & Failure Modes

Despite its robustness, the integration of USG in advanced semiconductor nodes presents severe physical challenges and potential failure modes [P3]. One of the most prevalent failure mechanisms is moisture absorption and subsequent chemical degradation [T1]. Because USG films deposited at lower thermal budgets (such as TEOS/O3 or low-temperature PECVD) can be somewhat porous, they readily absorb ambient water vapor [T1]. This absorbed water reacts with the silica network to form silanol (Si-OH) groups, which severely degrades the dielectric performance of the film, increasing its leakage current and dielectric constant [T1]. Furthermore, during subsequent thermal steps like rapid thermal annealing, this trapped moisture can desorb, generating high outgassing pressure that leads to film bubbling, cracking, or interfacial delamination from adjacent metal or barrier layers [P1, T1].

Another critical failure mode involves mechanical stress accumulation and cracking [P1, P3]. Thermal expansion mismatch between the silicon substrate, copper interconnects, and the USG dielectric layer generates massive internal stress during thermal cycling [P1, P3]. USG typically exhibits compressive stress when deposited on silicon, but excessive thickness or extreme thermal budgets can drive this stress to critical limits, causing wafer warpage and film peeling [P3]. In advanced packaging, where thick USG layers are used alongside copper through-silicon vias (TSVs) or hybrid bonding pads, the stress mismatch can drive crack propagation along the weaker interfaces between USG and adjacent low-k or metal barrier materials [P1, A1].

Additionally, USG films are susceptible to pattern-dependent defects during CMP (Engineering Practice). In structures integrating both dense active regions and wide isolation trenches filled with USG, differences in polish rates can lead to localized "dishing" and "erosion" of the dielectric, impacting the final planarization quality [P1]. Finally, during the dry etching of high-aspect-ratio contacts through USG, variations in film density can cause micro-trenching, etch-stop issues, or the "reactive ion etching (RIE) lag" effect, where narrow features etch significantly slower than wider ones due to transport limitations of reactive fluorine species [P2].

Technology Node Evolution

The role and integration of USG have undergone a dramatic transformation as the industry scaled from planar transistors at the 28nm Planar Flow to three-dimensional architectures at the 14nm FinFET and 7nm FinFET nodes, and onward to gate-all-around (GAA) nanosheets [T3].

The 28nm Planar Node

At the 28nm Planar Flow, USG was heavily utilized as a bulk dielectric for shallow trench isolation (STI) to isolate active areas [A2], and as a primary interlayer dielectric (ILD) or PMD buffer layer [T1]. In the BEOL stack, the industry had already begun transitioning from USG (k ≈ 4.1) and FSG (k ≈ 3.7) to low-k dielectric materials like carbon-doped oxide (SiOCH, k ≈ 2.9) to reduce resistance-capacitance (RC) delay and crosstalk noise [P2, T3]. However, USG was still widely retained as a thick, structurally robust passivation overcoat and as a hard mask to protect the delicate low-k materials during copper dual damascene patterning [P1, P2].

The 14nm FinFET Node

With the transition to the 14nm FinFET architecture, the physical aspect ratios of the silicon fins increased dramatically [T3]. Standard TEOS-based USG deposition struggled to fill the ultra-narrow, high-aspect-ratio gaps between adjacent fins without leaving keyhole voids (Engineering Practice). To overcome this limitation, process engineers integrated advanced flowable chemical vapor deposition (FCVD) techniques, where a liquid-like silicon-containing precursor is deposited and subsequently oxidized at a low temperature to form a seamless, void-free USG film within the fin structures [T1]. Additionally, the integration of high-k metal gate (HKMG) structures required USG to act as an ultra-pure sacrificial layer during replacement metal gate (RMG) processing (Engineering Practice).

The 7nm FinFET Node and Beyond

At the 7nm FinFET node and below, the extreme scaling of metal pitch necessitated the introduction of extreme ultraviolet (EUV) lithography and highly advanced self-aligned patterning schemes [T3]. In these nodes, the mechanical and chemical uniformity of USG became even more critical [P1]. While ultra-low-k (ULK) porous materials dominated the BEOL interconnect layers to combat RC delay [P2], USG was strategically utilized as an ultra-thin encapsulation liner [T1]. These thin USG "moisture barrier" or "buffer" liners shield the highly fragile porous ULK films from chemical attack by wet strippers and prevent the out-diffusion of moisture into the copper interfaces, directly mitigating device reliability degradation [P1, T1]. Furthermore, in 3D advanced packaging and through-silicon via (TSV) structures, USG is frequently integrated as a dual-taper passivation liner to isolate the copper TSV from the surrounding active silicon substrate [A1].

Related Processes

The implementation of USG is deeply interconnected with several adjacent process modules in the semiconductor flow:

• Chemical Mechanical Planarization (CMP): Because USG is highly rigid and mechanically stable compared to low-k materials, it serves as an exceptional structural "stop" or capping layer [P1]. In the copper dual damascene process, a thin cap of USG prevents the delicate low-k dielectric from collapsing or delaminating under the high downforce of the CMP tool [P1].
• Dry Etching: The patterning of USG relies on fluorine-based dry etching chemistries (such as CF4, CHF3, or C4F8) [P2]. USG exhibits highly controllable and predictable etch rates compared to porous low-k films, which are prone to micro-trenching, severe sidewall roughness, and chemical modification (plasma damage) when exposed to oxygen-containing or fluorine-rich ashing plasmas [P2].
• Wet Cleaning and Etching: USG is frequently etched or cleaned using diluted hydrofluoric acid (DHF) (Engineering Practice). Because its etch rate in DHF is highly dependent on its density and thermal history, DHF wet etching is often used as a metrology method to evaluate the quality and densification level of the deposited USG film [T1].
• Atomic Layer Deposition (ALD): For advanced nodes requiring atomic-scale thickness control, atomic layer deposition (ALD) is utilized to deposit ultra-thin conformal silicon dioxide films that act as starting surfaces or barrier liners before bulk USG deposition by PECVD or FCVD [P2].

Future Outlook

As the semiconductor industry advances toward 3D logic integration (such as complementary FETs or CFETs) and high-density compute-in-memory architectures, undoped silicate glass continues to find new applications [A2]. The push for heterogeneous integration and 3D chip stacking has revitalized the demand for high-quality USG [A1]. In hybrid bonding (such as copper-to-copper direct bonding), USG serves as the primary inorganic dielectric surface that undergoes low-temperature hydrophilic fusion bonding to join separate wafers before metal-to-metal annealing takes place (Engineering Practice). This requires USG surfaces with sub-nanometer roughness, extremely low defectivity, and precise control of residual hydrogen and silanol concentration to prevent void formation during the final thermal cycle (Engineering Practice).

Furthermore, in the field of silicon photonics and flexible optoelectronics, USG is being investigated as a cladding material to guide light or as a mechanical protective sheath for co-integrated semiconductor fibers [P3]. By leveraging the mechanical reliability and optical transparency of pure amorphous silica, next-generation devices can achieve higher physical flexibility and optical coupling efficiency [P3]. Thus, while low-k materials continue to scale in traditional interconnect lines, the structural purity and reliability of USG ensure its perpetual relevance as a cornerstone material for advanced electronic and optoelectronic systems [P1, P3].