Introduction
As integrated circuit scaling advanced deep into the sub-micron regime, parasitic resistance at the source, drain, and gate electrodes became a dominant bottleneck limiting device performance . To address this challenge, the semiconductor industry adopted the self-aligned silicide (salicide) process, which selectively converts exposed silicon surfaces into highly conductive transition metal silicides . This technique successfully minimizes the parasitic source/drain series resistance between the contact metal and the transistor channel .
Among the various silicides, cobalt silicide (principally in its stable $\text{CoSi}_2$ phase) emerged as a premier material for ultra large scale integration (ULSI) applications . Initially developed to overcome the scaling limitations of titanium silicide ($\text{TiSi}_2$) [P1, T1], cobalt silicide offers a unique combination of low bulk resistivity, excellent chemical stability, and compatibility with advanced microelectronic processing [P3, A1].
Unlike titanium silicide, which suffers from a severe "narrow-line effect" where its resistance increases dramatically on sub-micron features due to nucleation constraints, the sheet resistance of cobalt silicide remains virtually independent of line width . Additionally, during its solid-state formation reaction, cobalt acts as the dominant diffusing species . This spatial diffusion characteristic significantly reduces lateral encroachment of the silicide under oxide or nitride spacer structures, lowering the risk of electrical shorting between the gate and source/drain regions . Consequently, understanding the physical mechanisms, process dependencies, and integration challenges of cobalt silicide is essential for modern semiconductor manufacturing .
Physics & Mechanism
The formation of cobalt silicide is governed by solid-state diffusion, phase transformation thermodynamics, and interface kinetics [P1, P3, A1]. When metallic cobalt is deposited onto a monocrystalline silicon substrate and subjected to thermal energy, a series of solid-phase reactions occur [P1, A1]. The driving force for these reactions is the minimization of the system's Gibbs free energy (Engineering Practice).
Phase Transformation Sequence
The cobalt-silicon (Co-Si) binary system features three sequential phases that form during thermal processing [P1, A1]:
- Dicobalt Silicide ($\text{Co}_2\text{Si}$): This is the first phase to nucleate at lower temperatures when cobalt atoms begin diffusing into the silicon lattice .
- Cobalt Monosilicide ($\text{CoSi}$): As the temperature increases or the reaction time is extended, the film completely transforms into the intermediate monosilicide phase ($\text{CoSi}$), which exhibits a higher electrical resistivity [P3, A1].
- Cobalt Disilicide ($\text{CoSi}_2$): At elevated temperatures, the monosilicide phase reacts with the remaining silicon to form the thermodynamically stable, highly conductive disilicide phase ($\text{CoSi}_2$) [P1, P3, A1].
The crystallography of the final $\text{CoSi}_2$ phase is highly compatible with the silicon substrate . $\text{CoSi}_2$ possesses a cubic fluorite crystal structure with a lattice constant very close to that of silicon, enabling epitaxial or near-epitaxial growth interfaces that exhibit low interfacial energy and high thermal stability . To analyze the electronic band structures of such silicides, solid-state physicists rely on Bloch's theorem, which describes the wavefunctions ($\psi$) of electrons in a periodic potential :
$$\psi_{n\mathbf{k}}(\mathbf{r}) = e^{j\mathbf{k}\cdot\mathbf{r}} u_{n\mathbf{k}}(\mathbf{r})$$
Here, $\mathbf{k}$ is the electron wavevector, $\mathbf{r}$ is the spatial coordinate, and $u_{n\mathbf{k}}(\mathbf{r})$ is a periodic function reflecting the translational symmetry of the crystal lattice defined by the direct lattice translation vectors :
$$\mathbf{R} = m\mathbf{a} + n\mathbf{b} + p\mathbf{c}$$
This periodic lattice match minimizes interfacial carrier scattering, facilitating low contact resistance at the metal-semiconductor interface (Engineering Practice).
Diffusion Kinetics and Silicon Consumption
During the formation of $\text{CoSi}_2$, the atomic diffusion mechanism is critical . In the $\text{Ti-Si}$ system, silicon is the dominant diffusing species, which frequently leads to the migration of silicon atoms out of the active areas and into the surrounding dielectric sidewalls, causing lateral encroachment . Conversely, in the cobalt silicide system, cobalt is the primary diffusing species during the formation of the lower-temperature phases, and silicon diffusion only becomes significant during the final transition to the disilicide phase . This limits lateral silicidation, allowing for tighter alignment margins [P1, T1].
However, the chemical reaction of $\text{CoSi}_2$ requires substantial silicon consumption [P1, T1]. For every unit thickness of deposited cobalt, a larger equivalent thickness of the underlying silicon substrate is consumed to form the stable disilicide phase . If this reaction is not carefully controlled, the front of the silicide interface can penetrate deep into the source/drain junctions, leading to severe junction leakage and diode degradation [P1, T1].
Wide-Bandgap Semiconductor Applications
The physics of cobalt silicide also extends to wide-bandgap materials such as silicon carbide ($\text{SiC}$) . When cobalt is reacted with $\text{4H-SiC}$ at elevated temperatures, it selectively reacts with the silicon component of the carbide lattice, forming a mixed phase of $\text{Co}_2\text{Si}$ and $\text{CoSi}$ .
This metallization alters the Schottky barrier height at the interface . On heavily doped n-type $\text{4H-SiC}$ substrates, high-temperature thermal processing drives a thinning of the depletion barrier, enabling carrier transport via thermionic field emission and field emission, resulting in stable Ohmic contacts . On p-type substrates, strong Fermi level pinning maintains a high barrier height, preserving rectifying (Schottky) contact behavior even after high-temperature treatments .
Process Principles
The performance, phase purity, and morphology of cobalt silicide depend strongly on the directional tuning of key process parameters during deposition and annealing [P3, A1].
Magnetron Sputter Deposition
The initial cobalt thin film is deposited via physical vapor deposition (PVD), specifically magnetron sputtering [P3, A1]. Because cobalt is a strongly ferromagnetic material, it presents a unique engineering challenge . The ferromagnetic target tends to capture and short-circuit the applied magnetic field, preventing the magnetic flux from penetrating into the plasma chamber . This suppresses the magnetron effect, reducing plasma confinement and lowering the sputtering rate .
To overcome this, engineers use high pass-through flux (PTF%) targets . The relationship between PTF, sputtering power, and discharge impedance is governed by the empirical DC planar magnetron sputtering current-voltage (I-V) relationship :
$$I = K V^n$$
where $I$ is the discharge current, $K$ is a system-dependent proportional constant, $V$ is the target voltage, and $n$ is an exponent representing the discharge impedance .
- Increasing PTF%: Directionally increases the magnetic flux intensity at the target surface, lowering the discharge impedance (which increases the exponent $n$), improving plasma ionization efficiency, and enhancing both deposition rate and film uniformity .
- Ar Pressure and Sputter Power: Elevating sputtering power increases the kinetic energy of the sputtered cobalt atoms, which impacts the density and initial stress of the deposited film .
[Low PTF% Target] --> Restricts Magnetic Flux --> High Impedance (Low n) --> Non-Uniform Film
[High PTF% Target] --> Maximizes Magnetic Flux --> Low Impedance (High n) --> Smooth, Uniform Film
Rapid Thermal Processing (RTP)
The conversion of the deposited cobalt film into low-resistivity $\text{CoSi}_2$ is typically carried out using a two-step rapid thermal processing (RTP) scheme :
- First Annealing Step (RTP1): Performed at moderate temperatures, this step promotes the solid-state reaction of cobalt with silicon to form the intermediate $\text{CoSi}$ phase [P1, A1]. The temperature must be high enough to initiate interdiffusion but low enough to prevent excessive silicon consumption and lateral encroachment [P1, T1].
- Selective Chemical Etching: Following RTP1, a selective wet etch (typically using acid mixtures) is applied to remove the unreacted cobalt from the dielectric isolation regions (e .g., spacer oxide or shallow trench isolation) without attacking the newly formed silicide [P1, T2, A1].
- Second Annealing Step (RTP2): Conducted at a higher temperature, this step drives the phase transformation from the highly resistive $\text{CoSi}$ phase to the low-resistivity $\text{CoSi}_2$ phase [P1, P3, A1]. If the temperature during RTP2 is too low, the transformation remains incomplete, leaving high-resistivity residual monosilicide phases [P1, P3, A1]. Conversely, if the temperature is too high, it triggers thermal agglomeration of the thin silicide film .
Nanosecond Laser Annealing
As device dimensions scale down, conventional rapid thermal annealing (RTA) treatments struggle with the narrow process margins of ultra-shallow junctions . Advanced integration utilizes nanosecond- to microsecond-scale pulsed laser annealing to achieve selective, solid-phase silicidation .
- Pulsed Energy Delivery: By adjusting the laser pulse duration and energy density, engineers can drive the direct solid-state transition from cobalt to the $\text{CoSi}_2$ phase in a single step, bypassing the intermediate nucleation obstacles of the $\text{CoSi}$ phase .
- Melting Threshold Margins: The laser energy density must be tightly controlled (Engineering Practice). If the energy density is too low, the solid-state conversion is incomplete, leaving highly resistive unreacted or intermediate phases . If the energy density exceeds the material's melting threshold, local liquid-phase melting and subsequent re-solidification occur, inducing mechanical stress, cracking, and interface non-planarity .
Challenges & Failure Modes
Implementing cobalt silicide in sub-micron technologies is associated with several physical and chemical failure modes that degrade device yield and performance [P1, T1, A1].
Process Deviation Physical Mechanism Electrical Failure Mode
---------------- ------------------ ---------------------
Excessive Thermal Budget ---------> Thermal Agglomeration / Pinning ---------> Sheet Resistance Spike
Excessive Si Consumption ---------> Deep Junction Penetration --------------> Junction Leakage / Diode Shorting
Low Temperature / Low Laser Energy -> Incomplete Phase Transformation --------> High Contact Resistance (CoSi Residue)
Thermal Agglomeration
Thin films of $\text{CoSi}_2$ are thermodynamically unstable at high temperatures . When subjected to excessive thermal budgets during post-silicidation steps (such as intermetal dielectric deposition and curing), the silicide film tends to agglomerate . Driven by the reduction of surface and interfacial free energy, the continuous thin film breaks up, forming isolated islands and exposing the underlying silicon substrate . This morphological degradation causes a massive spike in sheet resistance and contact resistance (Engineering Practice). The risk of agglomeration increases severely as the line width narrows and the silicide film thickness is scaled down .
Junction Leakage and Shallow Junction Damage
Because $\text{CoSi}_2$ formation consumes a significant amount of the underlying silicon, integrating this material with shallow source/drain junctions is a major challenge [P1, T1]. If the initial cobalt layer is too thick or the thermal budget is excessive, the silicide interface can consume the entire junction depth [P1, T1]. This physical penetration of the metallurgical junction allows the highly conductive silicide to directly contact the oppositely doped substrate, leading to high junction leakage currents and device failure [P1, T1].
Residual Highly Resistive Phases
If the thermal budget of the RTP2 step (or the energy density of a pulsed laser anneal) is insufficient, the phase transformation from the monosilicide to the disilicide phase remains incomplete [P1, P3, A1]. The presence of residual $\text{CoSi}$—which exhibits significantly higher electrical resistivity compared to the stable $\text{CoSi}_2$ phase—prevents the contact from achieving its targeted low resistance, degrading the current-driving capability of the transistor [P1, P3, A1].
Mechanical Stress and Interface Roughness
The difference in thermal expansion coefficients between cobalt silicide, the silicon substrate, and the surrounding dielectric spacers generates substantial mechanical stress during high-temperature processing . This stress can lead to defect generation, dislocation formation, and interface roughness . An uneven silicide/silicon interface leads to localized electric field crowding, which lowers the localized junction breakdown voltage and degrades the reliability of the gate dielectric [T1, A1].
Technology Node Evolution
The adoption and adaptation of cobalt silicide reflect the historical push toward smaller, faster, and more power-efficient devices [P1, P3, T2].
The 28nm Planar Node
At the 28nm Planar Flow, planar MOSFETs encountered severe series resistance limitations (Engineering Practice). Cobalt silicide became the standard material for contact silicidation, fully replacing titanium silicide due to its immunity to the narrow-line effect [P1, T1]. The self-aligned process was highly mature, utilizing a two-step RTA process with selective wet-strip chemistries to ensure low sheet resistance on gates and source/drain regions [P1, T2].
To prevent silicidation in specific areas where resistors or electrostatic discharge (ESD) protection devices were located, a salicide block (SAB) oxide layer was patterned prior to cobalt deposition . During the silicidation process, the gate work function and surface potentials remained well-behaved, governed by the flat-band voltage relationship :
$$V_{fb} = \psi_g - \psi_s$$
where $\psi_g$ represents the work function of the gate and $\psi_s$ is the semiconductor work function .
The 14nm FinFET Node
With the transition to three-dimensional architectures at the 14nm FinFET, silicide integration had to adapt to highly non-planar geometries (Engineering Practice). Sputtering cobalt uniformly over high-aspect-ratio 3D fins required optimization of target PTF% and advanced collimator or ionized PVD technologies to ensure conformal coverage of the fin sidewalls .
The extremely narrow silicon fins significantly restricted the volume of silicon available for silicide reactions (Engineering Practice). Excessive silicon consumption on such small volumes risked consuming the entire fin, leading to structural voiding and severe electrical open failures [P1, T1]. Consequently, the industry optimized the thermal budget, moving toward ultra-short RTA steps to control the reaction front .
The 7nm FinFET Node and Beyond
At the 7nm FinFET and more advanced nodes, the contact dimensions shrunk to the sub-10nm scale (Engineering Practice). At these dimensions, cobalt silicide encountered physical scaling limits . The extremely thin films became highly susceptible to thermal agglomeration, and the contact resistance began to be dominated by the interface transition barrier rather than the bulk silicide resistance [T1, A2].
To sustain scaling, the industry began transitioning to nickel-platinum silicide ($\text{NiPtSi}$) and eventually toward direct cobalt plug contacts and ruthenium-based metallization schemes .
Furthermore, to optimize front-side routing density, advanced architectures developed backside power delivery networks (BSPDN) . In these schemes, back-side contact structures are formed to connect directly to the source/drain regions from the rear of the wafer . This process uses placeholder structures to prevent active area erosion during back-side processing, maximizing the contact area and minimizing the contact resistance .
Related Processes
The successful integration of cobalt silicide requires seamless coordination with several adjacent front end of line (FEOL) and middle of line (MOL) process steps .
[Lithography & Contact Etch]
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[Pre-Clean / HF Dip] ──> Removes Native Oxide
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[PVD Cobalt Sputtering] ──> High PTF% Target Magnetron Sputter
│
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[RTP1 Annealing] ──> Forms Highly Resistive CoSi Phase
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[Selective Wet Clean] ──> Strips Unreacted Cobalt (SPM/HPM)
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[RTP2 Annealing] ──> Converts to Low-Resistivity CoSi2 Phase
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[Intermetal Dielectric] ──> Deposition of USG/PSG
Lithography and Etching
Before cobalt deposition, contact holes must be patterned and etched through the dielectric layers . In advanced lithography, a bottom anti-reflective coating (BARC) is applied to control light reflection and prevent standing wave defects . This ensures that the contact openings are precisely defined, preventing alignment errors that could lead to silicide bridging to adjacent structures [P1, T2].
Surface Pre-Cleaning
Prior to cobalt sputtering, any native oxide ($\text{SiO}_2$) on the exposed silicon contact regions must be completely removed . Because oxide acts as a diffusion barrier, even a thin native oxide layer can inhibit the solid-state reaction between cobalt and silicon, leading to incomplete silicidation, high contact resistance, or voiding . This is typically accomplished via specialized dry or wet clean steps, such as a dilute hydrofluoric acid (HF) dip or an anhydrous HF vapor etch (Engineering Practice).
Wet Chemical Clean / Selective Strip
Following the first low-temperature rapid thermal processing (RTP1) step, the unreacted cobalt must be selectively removed [P1, T2, A1]. This is performed using wet chemical cleaning processes [P1, T2]. Mixtures such as sulfuric acid-hydrogen peroxide (SPM) or hydrochloric acid-hydrogen peroxide (HPM) are formulated to oxidize and dissolve the unreacted metallic cobalt from the dielectric oxide/nitride isolation surfaces, while leaving the reacted $\text{CoSi}$ or $\text{Co}_2\text{Si}$ film in the contact holes intact [P1, T2, A1].
Intermetal Dielectric Isolation
Once the low-resistance $\text{CoSi}_2$ phase is formed during RTP2, the structure is encapsulated in intermetal dielectric layers . Materials such as undoped silicate glass (USG) or phosphosilicate glass (PSG) are deposited to insulate the contacts and provide a flat surface for subsequent metal routing layers . The thermal budget of these dielectric depositions must be carefully managed to prevent the thermal agglomeration of the underlying thin cobalt silicide films .
Future Outlook
As the semiconductor industry advances toward nanosheet field-effect transistors, forksheet transistors, and 3D complementary metal-oxide-semiconductor (CMOS) configurations, the role of contact metallization continues to evolve .
Nanosecond and Picosecond Laser Processing
To completely decouple the thermal budget of the contact formation from the rest of the device, ultra-fast laser annealing is gaining traction . Applying nanosecond or picosecond laser pulses allows for localized heating of the contact interface . This approach drives the phase transition to the low-resistance $\text{CoSi}_2$ phase while keeping the bulk wafer temperature low, preventing dopant deactivation in shallow junctions [P1, A1].
Backside Contact Schemes and 3D Integration
The implementation of backside contact structures is a major paradigm shift in advanced scaling . By routing power delivery to the back side of the wafer, the front side is reserved entirely for signal routing . Designing these contacts using specialized placeholder structures allows for a wider contact profile, increasing the contact area to the source/drain regions and mitigating contact resistance issues .
Novel Substrate Co-Integration
Beyond silicon, cobalt silicide shows potential in emerging high-power and high-frequency electronics built on silicon carbide and other wide-bandgap substrates . Refining the high-temperature solid-phase reactions of cobalt on these substrates will enable low-resistance self-aligned contacts, simplifying the process integration for next-generation power devices .