Guide to Salicide Block (SAB): Principles, Process Integration, and Advanced Node Evolution

Introduction

The self-aligned silicide process has been a core module in complementary metal-oxide-semiconductor (CMOS) integration. This self-aligned silicide process has been coined salicide [T2]. The primary goal of silicidation is to significantly lower the sheet and contact resistance of active source, drain, and gate regions in metal-oxide-semiconductor field-effect transistors (MOSFETs). By reacting a transition metal directly with exposed silicon areas, a low-resistivity metal silicide layer is formed self-aligned to the gate without requiring dedicated contact lithography alignment steps.

However, in integrated circuit manufacturing, specific silicon areas must remain unsilicided. Uncontrolled silicidation on passive components or protection devices causes severe electrical degradation or junction breakdown. To address this requirement, process engineers implement a salicide block (SAB) module. A salicide block is a patterned dielectric thin film—typically composed of silicon dioxide (SiO2), silicon nitride (Si3N4), or oxynitride stacks—that acts as a physical and chemical diffusion barrier, preventing deposited transition metals from reacting with underlying silicon during subsequent thermal processing steps.

Several critical circuit structures require an SAB layer:

• Electrostatic Discharge (ESD) Protection: ESD protection structures, such as ballast resistors and protection diodes, require adequate internal ballasting resistance to distribute transient currents uniformly. Fully silicided diffusion areas exhibit low resistance, leading to localized current crowding and premature thermal breakdown.
• Precision Analog and RF Resistors: Analog circuits depend on passive resistors with precise sheet resistance and minimal voltage coefficients. Removing the high-conductivity silicide from these active or polysilicon regions allows the resistor to retain its intended resistivity.
• Embedded Non-Volatile Memory: In structures such as embedded resistive random-access memory or floating-gate memory cell selectors, keeping specific diffusion nodes unsilicided minimizes junction leakage and provides controlled contact coupling to memory electrodes.

Physics and Chemical Mechanisms of Silicidation and Blocking

Understanding how an SAB layer functions requires evaluating solid-state chemical kinetics and thin-film interdiffusion. When a thin transition metal film (such as nickel, cobalt, or titanium) is deposited onto clean silicon and subjected to thermal energy, solid-state interdiffusion occurs across the metal-silicon interface. This reaction is thermodynamically driven by the reduction of interfacial free energy and chemical potential differences between the metal and the semiconductor.

As temperature increases during rapid thermal annealing, intermetallic phases nucleate and evolve sequentially based on thermal budget:

1. Initial Metal-Rich Phases: At lower reaction temperatures, metal-rich phases nucleate (e.g., Ni2Si or precursor C49-TiSi2). These phases generally possess higher electrical resistivity.
2. Low-Resistivity Monosilicide Phase: At intermediate temperatures, the system transitions to the target low-resistivity phase (such as NiSi or C54-TiSi2), offering an optimal balance between low contact resistance and controlled silicon consumption.
3. High-Temperature Disilicide Phase: Excessively high thermal budgets drive the reaction toward silicon-rich disilicide phases (such as NiSi2), which can induce morphological agglomeration and increased junction leakage.

The primary physical mechanism of the SAB dielectric layer is to serve as an amorphous, high-density diffusion barrier that interrupts this interdiffusion pathway. The atomic structure of the SAB dielectric contains strong covalent bonds that resist reaction with transition metals at typical annealing temperatures. Consequently, metal atoms are blocked from diffusing downward into the silicon, and silicon atoms cannot migrate upward into the metal film, suppressing silicide formation in masked regions.

From a device physics standpoint, the presence or absence of the silicide layer alters the electronic band structure at the contact interface. At a direct metal-semiconductor contact, periodic crystal symmetry terminates, giving rise to metal-induced gap states and establishing a Schottky barrier height. Low-work-function or mid-gap silicides lower the effective contact resistance (R_c) for majority carriers. Conversely, in regions protected by the SAB layer, the semiconductor retains its baseline interface characteristics and carrier concentration, maintaining the high sheet resistance (R_sh) necessary for analog resistors and ESD ballast structures.

Process Principles and Parameter Interactions

The fabrication of a salicide block involves a sequence of dielectric deposition, photolithographic patterning, high-selectivity dry etching, and post-etch cleaning steps.

Dielectric Deposition Kinetics

The SAB layer is typically deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD). In advanced logic nodes, plasma-enhanced atomic layer deposition (PEALD) is favored because it separates surface-limited chemical reactions into sequential precursor adsorption and plasma-assisted oxidation steps. This enables the growth of high-density, conformal films at low thermal budgets.

The physical properties of the deposited SAB film depend on deposition parameters such as plasma power, exposure time, and substrate temperature. When process temperature or plasma power is reduced, incomplete precursor ligand removal can occur, which artificially increases growth-per-cycle. However, these low-temperature films tend to be chemically porous and contain higher impurity concentrations, degrading their barrier efficiency. Conversely, increasing plasma power or exposure time densifies the film, improving barrier performance, though excessive plasma energy risks inducing sub-surface lattice damage on exposed active silicon regions.

Patterning and Etching Dynamics

Once the SAB dielectric is deposited, photolithography defines the regions where the block layer must be retained. Subsequently, a dry etching process removes the unmasked dielectric from active transistor areas where silicide is required. The etching chemistry must exhibit high selectivity toward the SAB dielectric relative to the underlying silicon substrate and gate sidewall spacers. During dry etching, passivation layer formation from surface oxidation and from etch byproducts arriving from the plasma as well as being directly redeposited from the bottom surface onto sidewalls can influence profile control [T1]. If etch selectivity to silicon is inadequate, plasma etching can recess the source/drain regions, increasing parasitic spreading resistance (R_sp) and causing threshold voltage variations.

Following dry etching, wet chemical cleaning is performed to remove fluorinated polymers and post-etch residues. If cleaning chemical temperature or duration is insufficient, residual polymers block metal-silicon contact, causing un-silicided spot defects or high contact resistance. However, over-aggressive wet cleaning can erode adjacent sidewall spacers or undercut the SAB mask edge, creating potential bridging paths between the gate and source/drain contacts.

Challenges & Failure Modes

Integrating a salicide block into high-density CMOS flows introduces several physical and chemical failure modes that require careful process control:

• Blistering and Delamination: Dielectric films deposited via ALD using water or ozone precursors can trap hydroxyl (-OH) or hydrogen-rich species at the dielectric-silicon interface. During subsequent high-temperature rapid thermal annealing, these volatile species outgas, generating localized vapor pressure that causes mechanical blistering and delamination. Deposited metal can then seep under blisters, forming localized silicide shorts.
• Silicide Spiking and Pinholes: Micro-cracks, pinholes, or localized thinning over tall gate topography destroy the diffusion barrier integrity. During thermal annealing, metal atoms rapidly diffuse through these pinholes, forming deep silicide spikes that penetrate shallow source/drain p-n junctions and dramatically increase junction leakage current.
• Phase Degradation and Agglomeration: Nickel-based monosilicide (NiSi) is thermally sensitive. Uncontrolled thermal exposure during downstream back-end dielectric processing can cause NiSi to agglomerate into isolated islands or convert to the high-resistivity NiSi2 phase, escalating line and contact resistance.

Technology Node Evolution

The implementation of the salicide block has undergone significant evolutionary shifts as the industry scaled from planar transistors down to complex 3D architectures.

Technology Node	Device Architecture	SAB Material & Deposition	Primary Integration Challenges
28nm	Planar High-K Metal Gate	PECVD SiO2 / Si3N4	Planar defect density, selectivity of dry etch over active silicon
14nm	3D FinFET	High-Conformality PEALD SiO2	3D fin sidewall coverage, shadowing effects, spacer erosion
7nm and beyond	Advanced FinFET / GAA Nanosheet	Selective ALD / Ultra-thin PEALD	High aspect ratio voids, thermal budget compatibility with HKMG

At the 28nm planar node, the SAB process was relatively straightforward. The topography was flat, allowing standard plasma-enhanced chemical vapor deposition (PECVD) to deposit a uniform layer of silicon dioxide or silicon nitride, which was then patterned using optical lithography and dry etching.

However, the transition to 3D vertical fin geometries introduced severe aspect ratio challenges. For 20-nm and 14-nm node technologies, multiple patterning immersion lithography has been widely applied in FinFET manufacturing [P3]. Standard PECVD techniques can suffer from poor step coverage on 3D features, resulting in thinner SAB films on vertical sidewalls compared to flat top regions. This non-uniformity increases the risk of barrier breakdown on fin sidewalls during thermal annealing. To address this, the industry adopted highly conformal PEALD processes to achieve atomic-scale thickness control over vertical surfaces. Furthermore, the integration of high-k metal gate (HKMG) structures constrained allowable downstream thermal budgets, requiring optimized low-temperature deposition processes.

Related Processes

The salicide block module operates in tight coordination with surrounding fabrication steps:

• Ion Implantation: Dopant species (e.g., arsenic, phosphorus, boron) implanted into source/drain regions modify silicidation reaction kinetics. Heavy dopant concentrations can retard silicide growth, requiring precise thermal budget tuning to achieve complete silicidation in exposed regions without degrading SAB integrity.
• Gate Patterning and Spacer Formation: Gate sidewall spacers establish the physical offset between the gate electrode and source/drain silicide. The SAB film must adhere securely to spacer dielectrics to prevent interface seeping and gate-to-source/drain bridging.
• Metal Deposition and Rapid Thermal Annealing: Sputtered metal films (Ni, Pt alloys, or Co) are converted to silicide via multi-step RTA. Annealing parameters dictate phase stability and minimize encroachment beneath SAB mask edges.
• Chemical Mechanical Planarization: Following selective stripping of unreacted metal, inter-layer dielectrics are deposited and planarized via CMP. The SAB layer must exhibit strong interfacial adhesion to withstand mechanical shear stress during polishing.

Future Outlook

As semiconductor scaling progresses beyond 3nm nodes toward nanosheet gate-all-around (GAA) and complementary FET (CFET) architectures, traditional lithography and etching schemes for SAB face severe overlay constraints. The extremely tight pitches of these advanced devices leave virtually no margin for alignment errors.

To address these challenges, researchers are evaluating area-selective atomic layer deposition (AS-ALD) techniques. Instead of depositing a continuous SAB film and patterning it via lithography and dry etching, AS-ALD utilizes surface chemical inhibitors to deposit dielectric barrier material selectively on target surfaces (such as gate spacers) while leaving active silicon regions exposed. This bottom-up approach offers a self-aligned, damage-free alternative for future advanced-node integration.