Dummy Gate in Replacement Metal Gates

A dummy gate is a temporary patterned gate in a gate-last replacement-metal-gate flow. It reserves the future gate location while surrounding structures are formed. The temporary material is later removed and the final gate stack is built in the opening; it is not the finished electrical gate [P1].

Why keep a temporary gate?

The placeholder fixes a geometry around which nearby transistor regions can be integrated. In the cited replacement-gate review, sacrificial polysilicon and the original dielectric are removed after surrounding films and planarization, then new gate materials are added. This is one documented sequence, not a universal material choice [P1].

Patterning and removal are different questions

Patterning the temporary gate and clearing the later opening are separate tasks. Removal has to create space for the final dielectric and electrode without assuming that the opening alone proves their electrical quality [P1].

The replacement-gate review also describes how the final stack faces a different thermal history from a gate built earlier. Any advantage depends on the actual materials, interfaces and subsequent processing [P1].

Locate it in the current Flow

The current 14nm FinFET topology names dummy a-Si deposition and dummy-gate patterning in its GATE module, with poly dummy removal much later in RMG. Many Steps intervene. Because those Step readings are not approved, this article links to the Flow overview to show the order, while the cited source supports the replacement mechanism [P1].

Keep the distinctions clear

A gate-first route introduces a functional stack earlier, so its ordering differs from this sacrificial-gate route. The dummy gate is removed; the final work-function metal remains in the device. Check the selected Flow's topology before applying this description elsewhere [P1].