28nm Planar FlowPreview

ntrol over the channel [T1]. This step follows surface preparation and plasma nitridation, which condition the Si surface by reducing native oxide, passivating dangling bonds, and modulating interfacial chemistry to suppress uncontrolled interfacial layer regrowth during subsequent high-k deposition [P2]. By inserting HfO2 at this point in the GATE module, the process flow ensures that the dielectric is formed before any high-temperature metal gate or work-function layers are introduced, thereby preserving dielectric integrity and enabling later work-function tuning [A2]. The deposited HfO2 film prepares a chemically stable and electrically dense dielectric platform for post-deposition annealing, which is required to densify the film, passivate defects, and stabilize the interface prior to TiN gate metal deposition [P3].

Physical and Chemical Deposition Mechanism

High-k HfO2 deposition is predominantly implemented using atomic layer deposition, which relies on sequential, self-limiting surface reactions to achieve monolayer-level thickness control and excellent uniformity across planar features [P1]. In each ALD cycle, a hafnium precursor chemisorbs onto reactive surface sites, followed by an oxidant pulse that removes organic ligands and forms Hf–O bonds, regenerating surface reactivity for the next cycle [P3]. The oxidizing strength of the oxygen source directly controls the completeness of ligand removal and the density of oxygen vacancies, which in turn affects fixed charge density and leakage behavior in the final device [P1]. From a device-physics perspective, increasing the dielectric constant through HfO2 allows the gate capacitance to remain high while increasing the physical thickness, thereby reducing direct tunneling probability according to quantum-mechanical barrier transmission models [T1].

Material and Method Selection Reasoning

HfO2 is selected as the gate dielectric because it combines a high dielectric constant, sufficient band offsets to silicon, and thermodynamic stability against silicon at gate processing temperatures, enabling aggressive equivalent oxide thickness scaling with manageable leakage current [T1]. Atomic layer deposition is chosen over other deposition techniques because its surface-reaction-limited growth minimizes thickness variability and ensures conformal coverage, which is critical for controlling threshold voltage and subthreshold swing in scaled planar devices [P2]. Process parameter interactions are governed by coupled thermodynamic and kinetic effects: stronger oxidants and higher thermal energy enhance oxidation completeness and film density, while simultaneously increasing the driving force for interfacial Si oxidation, which degrades equivalent capacitance density [P3]. Consequently, this step is engineered to balance oxidant reactivity and thermal activation so that bulk dielectric quality improves without excessive interfacial layer growth, setting favorable initial conditions for subsequent annealing treatments [P1].

28nm Node-Specific Considerations

At the 28nm planar node, gate length scaling places stringent requirements on electrostatic control and variability suppression, making precise equivalent oxide thickness control and low interface state density essential for yield and performance [T1]. Compared with earlier nodes, the allowable process window for high-k deposition is narrower because small variations in interfacial layer thickness translate directly into threshold voltage shifts and mobility degradation [P3]. Unlike later FinFET or GAA architectures, the planar geometry relies more heavily on gate dielectric quality rather than three-dimensional electrostatics, increasing the sensitivity to HfO2 bulk defects and interface charges [T1]. Therefore, the High-k HfO2 Deposition step at 28nm is optimized not for extreme conformality but for defect minimization, interfacial stability, and compatibility with subsequent metal gate integration [P2].