Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
7nm FinFET Metal-Two Interconnect Integration: Process Flow Principles and ESL Deposition Mechanics
Role in the Complete Flow The metal-two (M2) interconnect module in a 7nm FinFET process flow occupies a critical position in the back-end-of-line (BEOL) archit
14nm FinFET Metal-Two Interconnect Integration: Process Flow, Physics, and Module Dependencies
Role in the Complete Flow In a 14nm FinFET logic technology, the metal-two (M2) interconnect module occupies a pivotal position in the back-end-of-line (BEOL) s
40nm BSI CMOS Image Sensor Frontside Deep-Trench Isolation Process Flow: Integration Principles, Device Physics, and Module Dependencies
Role in the Complete Flow The frontside deep-trench isolation (F_DTI) module in a 40nm BSI CMOS Image Sensor sits at a critical junction between front-end devic
28nm Planar Shallow Trench Isolation Process Flow: Principles, Integration Logic, and Mechanisms
Role in the Complete Flow The 28nm Planar shallow trench isolation module is one of the earliest structural-defining steps in the entire 28nm Planar process flo
28nm Planar Replacement Metal Gate Integration Process Flow: Principles, Mechanisms, and Integration Logic
Role in the Complete Flow The 28nm planar replacement metal gate (RMG) integration is a pivotal module that sits between front-end-of-line (FEOL) transistor for
28nm Planar Sidewall Spacer Integration Process Flow: Principles, Mechanisms, and Integration Logic
Role in the Complete Flow The sidewall spacer module sits at a critical junction in the 28nm Planar process flow, bridging gate stack formation and source/drain
40nm BSI CMOS Image Sensor Bond-Pad Integration: Process Flow Principles and Integration Logic
Role in the Complete Flow In a 40nm BSI CMOS Image Sensor, the bond-pad integration module sits at the top of the back-end-of-line (BEOL) interconnect stack and
40nm BSI CMOS Image Sensor Third Interlayer Dielectric Integration: Process Flow Principles and Device Physics
Role in the Complete Flow The third interlayer dielectric (ILD3) module in a 40nm BSI CMOS Image Sensor occupies a pivotal position within the back-end-of-line
40nm BSI CMOS Image Sensor Via-Four Integration Process Flow: Physical Mechanisms, Integration Logic, and Failure Propagation
Role in the Complete Flow The 40nm BSI CMOS Image Sensor via-four integration process flow occupies a critical position in the back-end-of-line (BEOL) interconn
40nm BSI CMOS Image Sensor Fifth Interlayer Dielectric Integration Process Flow: Principles, Mechanisms, and Integration Logic
Role in the Complete Flow In the 40nm backside-illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor process, the fifth interlayer diele
40nm BSI CMOS Image Sensor Metal-Six Interconnect Integration: Process Flow Principles and Integration Logic
Role in the Complete Flow In a 40nm BSI CMOS Image Sensor process flow, the metal-six (MET6) interconnect module serves as one of the uppermost wiring tiers, br
40nm BSI CMOS Image Sensor Backside Passivation Integration: Process Flow Principles and Device Physics
Role in the Complete Flow In a 40nm BSI CMOS Image Sensor (complementary metal oxide semiconductor image sensor) process flow, the backside passivation (BKPAS)